DS1220AB/AD
16k Nonvolatile SRAM
www.dalsemi.com
FEATURES
10 years minimum data retention in the
absence of external power
Data is automatically protected during power
loss
Directly replaces 2k x 8 volatile static RAM
or EEPROM
Unlimited write cycles
Low-power CMOS
JEDEC standard 24-pin DIP package
Read and write access times as fast as 100 ns
Lithium energy source is electrically
disconnected to retain freshness until power
is applied for the first time
Full ±10% V
CC
operating range (DS1220AD)
Optional ±5% V
CC
operating range
(DS1220AB)
Optional industrial temperature range of
-40°C to +85°C, designated IND
PIN ASSIGNMENT
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
VCC
A8
A9
WE
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
24-Pin ENCAPSULATED PACKAGE
720-mil EXTENDED
PIN DESCRIPTION
A0-A10
DQ0-DQ7
CE
WE
OE
V
CC
GND
- Address Inputs
- Data In/Data Out
- Chip Enable
- Write Enable
- Output Enable
- Power (+5V)
- Ground
DESCRIPTION
The DS1220AB and DS1220AD 16k Nonvolatile SRAMs are 16,384-bit, fully static, nonvolatile SRAMs
organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and
control circuitry which constantly monitors V
CC
for an out-of-tolerance condition. When such a condition
occurs, the lithium energy source is automatically switched on and write protection is unconditionally
enabled to prevent data corruption. The NV SRAMs can be used in place of existing 2k x 8 SRAMs
directly conforming to the popular bytewide 24-pin DIP standard. The devices also match the pinout of
the 2716 EPROM and the 2816 EEPROM, allowing direct substitution while enhancing performance.
There is no limit on the number of write cycles that can be executed and no additional support circuitry is
required for microprocessor interfacing.
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DS1220AB/AD
READ MODE
The DS1220AB and DS1220AD execute a read cycle whenever WE (Write Enable) is inactive (high) and
CE (Chip Enable) and OE (Output Enable) are active (low). The unique address specified by the 11
address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be
available to the eight data output drivers within t
ACC
(Access Time) after the last address input signal is
stable, providing that the CE and OE access times are also satisfied. If CE and OE access times are not
satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is
either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1220AB and DS1220AD execute a write cycle whenever the WE and CE signals are active (low)
after address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of
the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE . All address inputs
must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery
time (t
WR
) before another cycle can be initiated. The OE control signal should be kept inactive (high)
during write cycles to avoid bus contention. However, if the output drivers are enabled ( CE and OE
active) then WE will disable the outputs in t
ODW
from its falling edge.
DATA RETENTION MODE
The DS1220AB provides full functional capability for V
CC
greater than 4.75 volts and write protects by
4.5V. The DS1220AD provides full functional capability for V
CC
greater than 4.5 volts and write protects
by 4.25V. Data is maintained in the absence of V
CC
without any additional support circuitry. The
nonvolatile static RAMs constantly monitor V
CC
. Should the supply voltage decay, the NV SRAMs
automatically write protect themselves, all inputs become “don’t care,” and all outputs become high
impedance. As V
CC
falls below approximately 3.0 volts, a power switching circuit connects the lithium
energy source to RAM to retain data. During power-up, when V
CC
rises above approximately 3.0 volts,
the power switching circuit connects external V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds 4.75 volts for the DS1220AB and 4.5 volts for the
DS1220AD.
FRESHNESS SEAL
Each DS1220 device is shipped from Dallas Semiconductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first applied at a level of greater than V
TP
, the lithium
energy source is enabled for battery backup operation.
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DS1220AB/AD
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
-0.3V to +7.0V
0°C to 70°C; -40°C to +85°C for IND parts
-40°C to +70°C; -40°C to +85°C for IND parts
260°C for 10 seconds
∗
This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
DS 1220AB Power Supply Voltage
DS 1220AD Power Supply Voltage
Logic 1
Logic 0
SYMBOL MIN TYP MAX
V
CC
4.75 5.0
5.25
V
CC
4.50 5.0
5.50
V
IH
2.2
V
CC
V
IL
0.0
+0.8
(T
A
: See Note 10)
UNITS
V
V
V
V
NOTES
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Leakage Current
I/O Leakage Current
CE
≥
V
IH
≤
V
CC
Output Current @ 2.4V
Output Current @ 0.4V
Standby Current CE
=
2.2V
Standby Current CE
=
V
CC
-0.5V
Operating Current t
CYC
=200 ns
(Commercial)
Operating Current t
CYC
=200ns
(Industrial)
Write Protection Voltage
(DS1220AB)
Write Protection Voltage
(DS1220AD)
(V
CC
=5V
±
5% for DS1220AB)
(T
A
: See Note 10)
(V
CC
=5V
±
10% for DS1220AD)
UNITS
µ
A
µ
A
NOTES
SYMBOL MIN TYP MAX
-1.0
I
IL
+1.0
-1.0
+1.0
I
IO
I
OH
I
OL
I
CCS1
I
CCS2
I
CC01
I
CCO1
V
TP
V
TP
-1.0
2.0
5.0
3.0
10.0
5.0
75
85
4.5
4.25
4.62
4.37
4.75
4.5
mA
mA
mA
mA
mA
mA
V
V
CAPACITANCE
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL MIN TYP MAX
C
IN
5
10
C
I/O
5
12
(T
A
=25°C)
UNITS
pF
pF
NOTES
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DS1220AB/AD
AC ELECTRICAL CHARACTERISTICS
PARAMETER
(V
CC
=5.0V
±
5% for DS1220AB)
(T
A
:
See Note 10)
(V
CC
=5.0V
±
10% for DS1220AD)
NOTES
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from
Deselection
Output Hold from Address
Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High from WE
Output Active from WE
Data Setup Time
Data Hold Time
DS1220AB-100 DS1220AB-120
SYMBOL DS1220AD-100 DS1220AD-120 UNITS
MIN
MAX
MIN
MAX
t
RC
100
120
ns
t
ACC
100
120
ns
50
t
OE
60
ns
100
t
CO
120
ns
5
t
COE
5
ns
35
t
OD
35
ns
5
5
t
OH
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
5
100
75
0
0
10
35
5
40
0
10
5
120
90
0
0
10
35
5
50
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
12
13
5
4
4
12
13
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DS1220AB/AD
AC ELECTRICAL CHARACTERISTICS
PARAMETER
DS1220AB-150 DS1220AB-200
SYMBOL DS1220AD-150 DS1220AD-200 UNITS
MIN
MAX
MIN
MAX
t
RC
150
200
ns
t
ACC
150
200
ns
70
100
ns
t
OE
150
t
CO
200
ns
5
t
COE
5
ns
35
t
OD
35
ns
(cont’d)
NOTES
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High Z from
Deselection
Output Hold from Address
Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High Z from WE
Output Active from WE
Data Setup Time
Data Hold Time
5
5
t
OH
t
WC
t
WP
t
AW
t
WR1
t
WR2
t
ODW
t
OEW
t
DS
t
DH1
t
DH2
5
150
100
0
0
10
35
5
60
0
10
5
200
150
0
0
10
35
5
50
0
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
12
13
5
4
4
12
13
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