PRELIMINARY DATA SHEET
128M bits DDR SDRAM
EDD1216AASE (8M words
×
16 bits)
Description
The EDD1216AASE is a 128M bits Double Data Rate
(DDR) SDRAM organized as 2,097,154 words
×
16 bits
×
4 banks. Read and write operations are performed at
the cross points of the CK and the /CK. This high-
speed data transfer is realized by the 2 bits prefetch-
pipelined architecture. Data strobe (DQS) both for
read and write are available for high speed and reliable
data bus design. By setting extended mode register,
the on-chip Delay Locked Loop (DLL) can be set
enable or disable. It is packaged in 60-ball FBGA
(µBGA
) package.
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA ( BGA)
1
A
VSSQ DQ15 VSS
VDD
DQ0 VDDQ
2
3
4
5
6
7
8
9
B
DQ14 VDDQ DQ13
DQ2 VSSQ DQ1
DQ4 VDDQ DQ3
DQ6 VSSQ DQ5
LDQS VDDQ DQ7
LDM
/WE
/RAS
BA1
A0
A2
VDD
VDD
/CAS
/CS
BA0
A10
A1
A3
NC
C
DQ12 VSSQ DQ11
D
DQ10 VDDQ DQ9
Features
•
Power supply : VDDQ = 2.5V
±
0.2V
: VDD = 2.5V
±
0.2V
•
Data rate: 333Mbps/266Mbps (max.)
•
Double Data Rate architecture; two data transfers per
clock cycle
•
Bi-directional, data strobe (DQS) is transmitted
/received with data, to be used in capturing data at
the receiver
•
Data inputs, outputs, and DM are synchronized with
DQS
•
4 internal banks for concurrent operation
•
DQS is edge aligned with data for READs; center
aligned with data for WRITEs
•
Differential clock inputs (CK and /CK)
•
DLL aligns DQ and DQS transitions with CK
transitions
•
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
•
Data mask (DM) for write data
•
Auto precharge option for each burst access
•
SSTL_2 compatible I/O
•
Programmable burst length (BL): 2, 4, 8
•
Programmable /CAS latency (CL): 2, 2.5
•
Programmable output driver strength: normal/weak
•
Refresh cycles: 4096 refresh cycles/64ms
15.6µs maximum average periodic refresh interval
•
2 variations of refresh
Auto refresh
Self refresh
•
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
Document No. E0614E20 (Ver. 2.0)
Date Published March 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
E
DQ8 VSSQ UDQS
F
VREF VSS
UDM
/CK
CKE
A9
A7
A5
VSS
G
CK
H
NC
J
A11
K
A8
(AP)
L
A6
M
A4
(Top view)
A0 to A11
BA0, BA1
DQ0 to DQ15
UQQS/LDQS
/CS
/RAS
/CAS
/WE
UDM/LDM
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe
Column address strobe
Write enable
Input mask
Clock input
Differential clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Elpida
Memory, Inc. 2004-2005
EDD1216AASE
Ordering Information
Part number
EDD1216AASE-6B-E
EDD1216AASE-7A-E
Mask
version
A
Organization
(words
×
bits)
8M
×
16
Internal
banks
4
Data rate
Mbps (max.)
333
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR-333B (2.5-3-3)
DDR-266A (2-3-3)
Package
60-ball FBGA
(µBGA)
Part Number
E D D 12 16 A A SE - 6B - E
Elpida Memory
Type
D: Monolithic Device
Product Code
D: DDR SDRAM
Density / Bank
12: 128M / 4-bank
Bit Organization
16: x16
Voltage, Interface
A: 2.5V, SSTL_2
Die Rev.
Speed
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
Environment Code
E: Lead Free
Package
SE: FBGA (µBGA with back cover)
Preliminary Data Sheet E0614E20 (Ver. 2.0)
2
EDD1216AASE
CONTENTS
Description.....................................................................................................................................................1
Features.........................................................................................................................................................1
Pin Configurations .........................................................................................................................................1
Ordering Information......................................................................................................................................2
Part Number ..................................................................................................................................................2
Electrical Specifications.................................................................................................................................4
Block Diagram .............................................................................................................................................10
Pin Function.................................................................................................................................................11
Command Operation ...................................................................................................................................13
Simplified State Diagram .............................................................................................................................20
Operation of the DDR SDRAM ....................................................................................................................21
Timing Waveforms.......................................................................................................................................40
Package Drawing ........................................................................................................................................46
Recommended Soldering Conditions..........................................................................................................47
Preliminary Data Sheet E0614E20 (Ver. 2.0)
3
EDD1216AASE
Electrical Specifications
•
All voltages are referenced to VSS (GND).
•
After power up, wait more than 200 µs and then, execute power on sequence and CBR (Auto) refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter
Voltage on any pin relative to VSS
Supply voltage relative to VSS
Short circuit output current
Power dissipation
Operating ambient temperature
Storage temperature
Symbol
VT
VDD
IOS
PD
TA
Tstg
Rating
–1.0 to +3.6
–1.0 to +3.6
50
1.0
0 to +70
–55 to +125
Unit
V
V
mA
W
°C
°C
Note
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended Operating Conditions (TA = 0 to +70°C)
Parameter
Supply voltage
Symbol
VDD,
VDDQ
VSS,
VSSQ
VREF
VTT
VIH (DC)
VIL (DC)
VIN (DC)
VIX (DC)
VID (DC)
min.
2.3
0
0.49
×
VDDQ
VREF – 0.04
VREF + 0.15
–0.3
–0.3
0.5
×
VDDQ
−
0.2V
0.36
typ.
2.5
0
0.50
×
VDDQ
VREF
—
—
—
0.5
×
VDDQ
—
max.
2.7
0
0.51
×
VDDQ
VREF + 0.04
VDDQ + 0.3
VREF – 0.15
VDDQ + 0.3
Unit
V
V
V
V
V
V
V
2
3
4
Notes
1
Input reference voltage
Termination voltage
Input high voltage
Input low voltage
Input voltage level,
CK and /CK inputs
Input differential cross point
voltage, CK and /CK inputs
Input differential voltage,
CK and /CK inputs
0.5
×
VDDQ + 0.2V V
VDDQ + 0.6
V
5, 6
Notes: 1.
2.
3.
4.
5.
6.
VDDQ must be lower than or equal to VDD.
VIH is allowed to exceed VDD up to 3.6V for the period shorter than or equal to 5ns.
VIL is allowed to outreach below VSS down to –1.0V for the period shorter than or equal to 5ns.
VIN (DC) specifies the allowable DC execution of each differential input.
VID (DC) specifies the input differential voltage required for switching.
VIH (CK) min assumed over VREF + 0.18V, VIL (CK) max assumed under VREF – 0.18V if measurement.
Preliminary Data Sheet E0614E20 (Ver. 2.0)
4
EDD1216AASE
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Operating current (ACT-PRE)
Operating current
(ACT-READ-PRE)
Idle power down standby
current
Floating idle standby current
Quiet idle standby current
Active power down standby
current
Active standby current
Operating current
(Burst read operation)
Operating current
(Burst write operation)
Auto Refresh current
Self refresh current
Operating current
(4 banks interleaving)
Symbol
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
IDD6
IDD7A
Grade
max.
110
140
3
35
30
20
55
205
205
200
3
350
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Test condition
CKE
≥
VIH,
tRC = tRC (min.)
CKE
≥
VIH, BL = 4,
CL = 2.5,
tRC = tRC (min.)
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≥
VIH, /CS
≥
VIH
DQ, DQS, DM = VREF
CKE
≤
VIL
CKE
≥
VIH, /CS
≥
VIH
tRAS = tRAS (max.)
CKE
≥
VIH, BL = 2,
CL = 2.5
CKE
≥
VIH, BL = 2,
CL = 2.5
tRFC = tRFC (min.),
Input
≤
VIL or
≥
VIH
Input
≥
VDD – 0.2 V
Input
≤
0.2 V
BL = 4
Notes
1, 2, 9
1, 2, 5
4
4, 5
4, 10
3
3, 5, 6
1, 2, 5, 6
1, 2, 5, 6
1, 5, 6, 7
Notes: 1. These IDD data are measured under condition that DQ pins are not connected.
2. One bank operation.
3. One bank active.
4. All banks idle.
5. Command/Address transition once per one clock cycle.
6. DQ, DM and DQS transition twice per one clock cycle.
7. 4 banks active. Only one bank is running at tRC = tRC (min.)
8. The IDD data on this table are measured with regard to tCK = tCK (min.) in general.
9. Command/Address transition once every two clock cycle.
10. Command/Address stable at
≥
VIH or
≤
VIL.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V ± 0.2V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high current
Output low current
Symbol
ILI
ILO
IOH
IOL
min.
–2
–5
–15.2
15.2
max.
2
5
—
—
Unit
µA
µA
mA
mA
Test condition
VDD
≥
VIN
≥
VSS
VDDQ
≥
VOUT
≥
VSS
VOUT = 1.95V
VOUT = 0.35V
Note
Preliminary Data Sheet E0614E20 (Ver. 2.0)
5
