4Gb: x16 DDR4 SDRAM
Features
DDR4 SDRAM
EDY4016A - 256Mb x 16
Features
•
•
•
•
•
V
DD
= V
DDQ
= 1.2V ±60mV
V
PP
= 2.5V, –125mV/+250mV
On-die, internal, adjustable V
REFDQ
generation
1.2V pseudo open-drain I/O
T
C
of 0°C to 95°C
– 64ms, 8192-cycle refresh at 0°C to 85°C
– 32ms at 85°C to 95°C
8 internal banks: 2 groups of 4 banks each
8n-bit prefetch architecture
Programmable data strobe preambles
Data strobe preamble training
Command/Address latency (CAL)
Multipurpose register READ and WRITE capability
Write and read leveling
Self refresh mode
Low-power auto self refresh (LPASR)
Temperature controlled refresh (TCR)
Fine granularity refresh
Self refresh abort
Maximum power saving
Output driver calibration
Nominal, park, and dynamic on-die termination
(ODT)
Data bus inversion (DBI) for data bus
Command/Address (CA) parity
•
•
•
•
Databus write cyclic redundancy check (CRC)
Per-DRAM addressability
Connectivity test
JEDEC JESD-79-4 compliant
Options
1
• Revision
• FBGA package size
– 96-ball (7.5mm x 13.5mm)
• Timing – cycle time
– 0.625ns @ CL = 24 (DDR4-3200)
– 0.750ns @ CL = 19 (DDR4-2666)
– 0.833ns @ CL = 16 (DDR4-2400)
• Packaging
– Lead-free (RoHS-compliant) and hal-
ogen-free
Notes:
Marking
A
BG
-JD
-GX
-DR
-F
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1. Not all options listed can be combined to
define an offered product. Use the part
catalog search on http://www.micron.com
for available offerings.
2. Restricted and limited availability.
Table 1: Key Timing Parameters
Speed Grade
-JD
1
-GX
2
-DR
3
Notes:
Data Rate (MT/s)
3200
2666
2400
Target
t
RCD-
t
RP-CL
24-24-24
19-19-19
16-16-16
t
RCD
(ns)
t
RP
(ns)
CL (ns)
15.0
14.25
13.32
15.0
14.25
13.32
15.0
14.25
13.32
1. Backward compatible to 2666 CL = 20, 2400 CL = 18), 2133 CL = 16, 1866 CL = 14, 1600 CL = 12.
2. Backward compatible to 2400 CL = 17, 2133 CL = 15, 1866 CL = 13, 1600 CL = 11.
3. Backward compatible to 2133 CL = 15, 1866 CL = 13, 1600 CL = 11.
Table 2: Addressing
Parameter
Number of bank groups
Bank group address
256 Meg x 16
2
BG0
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
4Gb: x16 DDR4 SDRAM
Features
Table 2: Addressing (Continued)
Parameter
Bank count per group
Bank address in bank group
Row addressing
Column addressing
Page size
1
Note:
256 Meg x 16
4
BA[1:0]
32K (A[14:0])
1K (A[9:0])
2KB
1. Page size is per bank, calculated as follows:
Page size = 2
COLBITS
× ORG/8, where COLBIT = the number of column address bits and ORG = the number of
DQ bits.
Micron Memory Japan DDR4 Part Numbering
Figure 1: 4Gb DDR4 Part Numbers
E D Y 40 16 A A BG - JD - F- D
Manufacturer:
Micron Memory Japan
Packaging: Packaged device
Product Type: DDR4
Density: 4Gb
Organization: x16
Power Supply/V
DDQ
Term.: 1.2V
Die revision
Speed: JD = DDR4-3200 (24-24-24)
GX = DDR4-2666 (19-19-19)
DR = DDR4-2400 (16-16-16)
Package: FBGA
Packing Media: D = Dry pack (tray)
R = Tape and Reel
Packaging: Lead-free (RoHS-compliant)
and halogen-free
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
4Gb: x16 DDR4 SDRAM
Features
Contents
General Notes and Description .......................................................................................................................
Description ................................................................................................................................................
Industrial Temperature ...............................................................................................................................
General Notes ............................................................................................................................................
Definitions of the Device-Pin Signal Level ...................................................................................................
Definitions of the Bus Signal Level ...............................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Dimensions .......................................................................................................................................
State Diagram ................................................................................................................................................
Functional Description ...................................................................................................................................
RESET and Initialization Procedure .................................................................................................................
Power-Up and Initialization Sequence .........................................................................................................
RESET Initialization with Stable Power Sequence .........................................................................................
Uncontrolled Power-Down Sequence ..........................................................................................................
Programming Mode Registers .........................................................................................................................
Mode Register 0 ..............................................................................................................................................
Burst Length, Type, and Order .....................................................................................................................
CAS Latency ...............................................................................................................................................
Test Mode ..................................................................................................................................................
Write Recovery(WR)/READ-to-PRECHARGE ...............................................................................................
DLL RESET .................................................................................................................................................
Mode Register 1 ..............................................................................................................................................
DLL Enable/DLL Disable ............................................................................................................................
Output Driver Impedance Control ...............................................................................................................
ODT R
TT(NOM)
Values ..................................................................................................................................
Additive Latency .........................................................................................................................................
Write Leveling ............................................................................................................................................
Output Disable ...........................................................................................................................................
Termination Data Strobe .............................................................................................................................
Mode Register 2 ..............................................................................................................................................
CAS WRITE Latency ....................................................................................................................................
Low-Power Auto Self Refresh .......................................................................................................................
Dynamic ODT ............................................................................................................................................
Write Cyclic Redundancy Check Data Bus ....................................................................................................
Target Row Refresh Mode ............................................................................................................................
Mode Register 3 ..............................................................................................................................................
Multipurpose Register ................................................................................................................................
WRITE Command Latency When CRC/DM is Enabled .................................................................................
Fine Granularity Refresh Mode ....................................................................................................................
Temperature Sensor Status .........................................................................................................................
Per-DRAM Addressability ...........................................................................................................................
Gear-Down Mode .......................................................................................................................................
Mode Register 4 ..............................................................................................................................................
Post Package Repair Mode ..........................................................................................................................
Soft Post Package Repair Mode ....................................................................................................................
WRITE Preamble ........................................................................................................................................
READ Preamble ..........................................................................................................................................
READ Preamble Training ............................................................................................................................
Temperature-Controlled Refresh .................................................................................................................
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PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
4Gb: x16 DDR4 SDRAM
Features
Command Address Latency ........................................................................................................................ 51
Internal V
REF
Monitor ................................................................................................................................. 51
Maximum Power Savings Mode ................................................................................................................... 52
Mode Register 5 .............................................................................................................................................. 53
Data Bus Inversion ..................................................................................................................................... 54
Data Mask .................................................................................................................................................. 55
CA Parity Persistent Error Mode .................................................................................................................. 55
ODT Input Buffer for Power-Down .............................................................................................................. 55
CA Parity Error Status ................................................................................................................................. 55
CRC Error Status ......................................................................................................................................... 55
CA Parity Latency Mode .............................................................................................................................. 55
Mode Register 6 .............................................................................................................................................. 56
t
CCD_L Programming ................................................................................................................................. 57
V
REFDQ
Calibration Enable .......................................................................................................................... 57
V
REFDQ
Calibration Range ........................................................................................................................... 57
V
REFDQ
Calibration Value ............................................................................................................................ 57
Truth Tables ................................................................................................................................................... 58
NOP Command .............................................................................................................................................. 61
DESELECT Command .................................................................................................................................... 61
DLL-Off Mode ................................................................................................................................................ 61
DLL-On/Off Switching Procedures .................................................................................................................. 63
DLL Switch Sequence from DLL-On to DLL-Off ........................................................................................... 63
DLL-Off to DLL-On Procedure .................................................................................................................... 64
Input Clock Frequency Change ....................................................................................................................... 65
Write Leveling ................................................................................................................................................ 67
DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode ..................................... 68
Procedure Description ................................................................................................................................ 69
Write-Leveling Mode Exit ............................................................................................................................ 70
Command Address Latency ............................................................................................................................ 72
Low-Power Auto Self Refresh Mode ................................................................................................................. 77
Manual Self Refresh Mode .......................................................................................................................... 77
Multipurpose Register .................................................................................................................................... 79
MPR Reads ................................................................................................................................................. 80
MPR Readout Format ................................................................................................................................. 82
MPR Readout Serial Format ........................................................................................................................ 82
MPR Readout Parallel Format ..................................................................................................................... 83
MPR Readout Staggered Format .................................................................................................................. 84
MPR READ Waveforms ............................................................................................................................... 85
MPR Writes ................................................................................................................................................ 88
MPR WRITE Waveforms .............................................................................................................................. 89
MPR REFRESH Waveforms ......................................................................................................................... 90
Gear-Down Mode ........................................................................................................................................... 93
Maximum Power-Saving Mode ........................................................................................................................ 96
Maximum Power-Saving Mode Entry ........................................................................................................... 96
Maximum Power-Saving Mode Entry in PDA ............................................................................................... 97
CKE Transition During Maximum Power-Saving Mode ................................................................................. 97
Maximum Power-Saving Mode Exit ............................................................................................................. 97
Command/Address Parity ............................................................................................................................... 99
Per-DRAM Addressability .............................................................................................................................. 107
V
REFDQ
Calibration ........................................................................................................................................ 110
V
REFDQ
Range and Levels ........................................................................................................................... 111
V
REFDQ
Step Size ........................................................................................................................................ 111
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
4Gb: x16 DDR4 SDRAM
Features
V
REFDQ
Increment and Decrement Timing .................................................................................................. 112
V
REFDQ
Target Settings ............................................................................................................................... 116
Connectivity Test Mode ................................................................................................................................. 118
Pin Mapping ............................................................................................................................................. 118
Minimum Terms Definition for Logic Equations ......................................................................................... 119
Logic Equations for a x4 Device, When Supported ....................................................................................... 119
Logic Equations for a x8 Device, When Supported ....................................................................................... 120
Logic Equations for a x16 Device ................................................................................................................ 120
CT Input Timing Requirements .................................................................................................................. 120
Post Package Repair and Soft Post Package Repair ........................................................................................... 122
Post Package Repair ................................................................................................................................... 122
PPR Row Repair ......................................................................................................................................... 122
PPR Row Repair - Entry .......................................................................................................................... 122
PPR Row Repair – WRA Initiated (REF Commands Allowed) .................................................................... 123
PPR Row Repair – WR Initiated (REF Commands NOT Allowed) ............................................................... 124
sPPR Row Repair ....................................................................................................................................... 126
PPR/sPPR Support Identifier ...................................................................................................................... 128
Target Row Refresh Mode ............................................................................................................................... 129
ACTIVATE Command .................................................................................................................................... 130
PRECHARGE Command ................................................................................................................................ 131
REFRESH Command ..................................................................................................................................... 131
Temperature-Controlled Refresh Mode .......................................................................................................... 133
TCR Mode – Normal Temperature Range .................................................................................................... 133
TCR Mode – Extended Temperature Range ................................................................................................. 133
Fine Granularity Refresh Mode ....................................................................................................................... 135
Mode Register and Command Truth Table .................................................................................................. 135
t
REFI and
t
RFC Parameters ........................................................................................................................ 135
Changing Refresh Rate ............................................................................................................................... 138
Usage with TCR Mode ................................................................................................................................ 138
Self Refresh Entry and Exit ......................................................................................................................... 138
SELF REFRESH Operation .............................................................................................................................. 140
Self Refresh Abort ...................................................................................................................................... 142
Self Refresh Exit with NOP Command ......................................................................................................... 143
Power-Down Mode ........................................................................................................................................ 145
Power-Down Clarifications – Case 1 ........................................................................................................... 150
Power-Down Entry, Exit Timing with CAL ................................................................................................... 151
ODT Input Buffer Disable Mode for Power-Down ............................................................................................ 154
CRC Write Data Feature ................................................................................................................................. 156
CRC Write Data ......................................................................................................................................... 156
WRITE CRC DATA Operation ...................................................................................................................... 156
DBI_n and CRC Both Enabled .................................................................................................................... 157
DM_n and CRC Both Enabled .................................................................................................................... 157
DM_n and DBI_n Conflict During Writes with CRC Enabled ........................................................................ 157
CRC and Write Preamble Restrictions ......................................................................................................... 157
CRC Simultaneous Operation Restrictions .................................................................................................. 157
CRC Polynomial ........................................................................................................................................ 157
CRC Combinatorial Logic Equations .......................................................................................................... 158
Burst Ordering for BL8 ............................................................................................................................... 159
CRC Data Bit Mapping ............................................................................................................................... 159
CRC Enabled With BC4 .............................................................................................................................. 160
CRC with BC4 Data Bit Mapping ................................................................................................................ 160
CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1 ................................................................ 163
PDF: 09005aef85f537bf
4gb_ddr4_dram_2e0d.pdf - Rev. C 10/15 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2014 Micron Technology, Inc. All rights reserved.
