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FSPYC260R4

Power Field-Effect Transistor, 58A I(D), 200V, 0.031ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN

器件类别:分立半导体    晶体管   

厂商名称:International Rectifier ( Infineon )

厂商官网:http://www.irf.com/

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器件参数
参数名称
属性值
是否无铅
含铅
是否Rohs认证
不符合
厂商名称
International Rectifier ( Infineon )
包装说明
CHIP CARRIER, R-CBCC-N3
针数
3
Reach Compliance Code
compliant
ECCN代码
EAR99
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
200 V
最大漏极电流 (ID)
58 A
最大漏源导通电阻
0.031 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-CBCC-N3
JESD-609代码
e0
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
150 °C
封装主体材料
CERAMIC, METAL-SEALED COFIRED
封装形状
RECTANGULAR
封装形式
CHIP CARRIER
峰值回流温度(摄氏度)
NOT SPECIFIED
极性/信道类型
N-CHANNEL
最大脉冲漏极电流 (IDM)
200 A
认证状态
Not Qualified
表面贴装
YES
端子面层
TIN LEAD
端子形式
NO LEAD
端子位置
BOTTOM
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
FSPYC260R, FSPYC260F
Data Sheet
December 2001
Radiation Hardened, SEGR Resistant
N-Channel Power MOSFETs
Fairchild Star*Power Rad Hard
MOSFETs have been specifically
TM
developed for high performance
applications in a commercial or
military space environment. Star*Power MOSFETs offer the
system designer both extremely low r
DS(ON)
and Gate
Charge allowing the development of low loss Power
Subsystems. Star*Power FETs combine this electrical
capability with total dose radiation hardness up to 300K
RADS while maintaining the guaranteed performance for
SEE (Single Event Effects) which the Fairchild FS families
have always featured.
The Fairchild portfolio of Star*Power FETS includes a family
of devices in various voltage, current and package styles.
The Star*Power family consists of Star*Power and
Star*Power Gold products. Star*Power FETS are optimized
for total dose and r
DS(ON)
performance while exhibiting SEE
capability at full rated voltage up to an LET of 37. Star*Power
Gold FETS have been optimized for SEE and Gate Charge
providing SEE performance to 80% of the rated voltage for
an LET of 82 with extremely low gate charge characteristics.
This MOSFET is an enhancement-mode silicon-gate power
field effect transistor of the vertical DMOS (VDMOS)
structure. It is specifically designed and processed to be
radiation tolerant. The MOSFET is well suited for
applications exposed to radiation environments such as
switching regulation, switching converters, power
distribution, motor drives and relay drivers as well as other
power control and conditioning applications. As with
conventional MOSFETs these Radiation Hardened
MOSFETs offer ease of voltage control, fast switching
speeds and ability to parallel switching devices.
Reliability screening is available as either, TXV or Space
equivalent of MIL-S-19500.
Formerly available as type TA45211W.
Features
• 58A, 200V, r
DS(ON)
= 0.031Ω
• UIS Rated
• Total Dose
- Meets Pre-RAD Specifications to 100K RAD (Si)
- Rated to 300K RAD (Si)
• Single Event
- Safe Operating Area Curve for Single Event Effects
- SEE Immunity for LET of 36MeV/mg/cm
2
with
V
DS
up to 100% of Rated Breakdown and
V
GS
of 10V Off-Bias
• Dose Rate
- Typically Survives 3E9 RAD (Si)/s at 80% BV
DSS
- Typically Survives 2E12 if Current Limited to I
AS
• Photo Current
- 17nA Per-RAD (Si)/s Typically
• Neutron
- Maintain Pre-RAD Specifications
for 1E13 Neutrons/cm
2
- Usable to 1E14 Neutrons/cm
2
Symbol
D
G
S
Packaging
SMD2
Ordering Information
RAD LEVEL
10K
100K
100K
300K
300K
SCREENING LEVEL
Engineering samples
TXV
Space
TXV
Space
PART NUMBER/BRAND
FSPYC260D1
FSPYC260R3
FSPYC260R4
FSPYC260F3
FSPYC260F4
©2001 Fairchild Semiconductor Corporation
FSPYC260R, FSPYC260F Rev. B
FSPYC260R, FSPYC260F
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
FSPYC260R, FSPYC260F
Drain to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
Drain to Gate Voltage (R
GS
= 20kΩ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Continuous Drain Current
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Maximum Power Dissipation
T
C
= 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
T
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single Pulsed Avalanche Current, L = 100µH, (See Test Figure) . . . . . . . . . . . . . . . . . . . . . . I
AS
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
S
Pulsed Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
(Distance >0.063in (1.6mm) from Case, 10s Max)
Weight (Typical)
208
83
1.67
110
58
200
-55 to 150
300
3.3 (Typ)
W
W
W/
o
C
A
A
A
o
C
o
C
UNITS
V
V
A
A
A
V
200
200
58
37
200
±30
g
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
PARAMETER
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
BV
DSS
V
GS(TH)
TEST CONDITIONS
I
D
= 1mA, V
GS
= 0V
V
GS
= V
DS
,
I
D
= 1mA
T
C
= -55
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
T
C
= 25
o
C
T
C
= 125
o
C
MIN
200
-
2.0
1.0
-
-
-
-
-
-
-
-
-
-
-
V
GS
= 0V to 12V
V
DD
= 100V,
I
D
= 58A
-
-
-
V
GS
= 0V to 20V
V
GS
= 0V to 2V
I
D
= 58A, V
DS
= 15V
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
-
-
-
-
-
-
-
TYP
-
-
-
-
-
-
-
-
-
0.026
-
-
-
-
-
115
50
20
195
12
7.0
6500
1000
30
-
MAX
-
5.5
4.5
-
25
250
100
200
1.91
0.031
0.062
35
120
60
15
140
60
30
-
-
-
-
-
-
0.6
UNITS
V
V
V
V
µA
µA
nA
nA
V
ns
ns
ns
ns
nC
nC
nC
nC
nC
V
pF
pF
pF
o
C/W
Drain to Source Breakdown Voltage
Gate Threshold Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On-State Voltage
Drain to Source On Resistance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate Charge Source
Gate Charge Drain
Gate Charge at 20V
Threshold Gate Charge
Plateau Voltage
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Thermal Resistance Junction to Case
I
DSS
I
GSS
V
DS(ON)
r
DS(ON)12
t
d(ON)
t
r
t
d(OFF)
t
f
Q
g(12)
Q
gs
Q
gd
Q
g(20)
Q
g(TH)
V
(PLATEAU)
C
ISS
C
OSS
C
RSS
R
θ
JC
V
DS
= 160V,
V
GS
= 0V
V
GS
=
±30V
V
GS
= 12V, I
D
= 58A
I
D
= 37A,
V
GS
= 12V
V
DD
= 100V, I
D
= 58A,
R
L
= 1.72Ω, V
GS
= 12V,
R
GS
= 2.35Ω
©2001 Fairchild Semiconductor Corporation
FSPYC260R, FSPYC260F Rev. B
FSPYC260R, FSPYC260F
Source to Drain Diode Specifications
PARAMETER
Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
SYMBOL
V
SD
t
rr
Q
RR
T
C
= 25
o
C, Unless Otherwise Specified
MIN
PARAMETER
Drain to Source Breakdown Volts
Gate to Source Threshold Volts
Gate to Body Leakage
Zero Gate Leakage
Drain to Source On-State Volts
Drain to Source On Resistance
NOTES:
1. Pulse test, 300µs Max.
2. Absolute value.
3. In situ Gamma bias must be sampled for both V
GS
= 12V, V
DS
= 0V and V
GS
= 0V, V
DS
= 80% BV
DSS
.
(Note 3)
(Note 3)
(Notes 2, 3)
(Note 3)
(Notes 1, 3)
(Notes 1, 3)
SYMBOL
BV
DSS
V
GS(TH)
I
GSS
I
DSS
V
DS(ON)
r
DS(ON)12
TEST CONDITIONS
V
GS
= 0, I
D
= 1mA
V
GS
= V
DS
, I
D
= 1mA
V
GS
=
±30V,
V
DS
= 0V
V
GS
= 0, V
DS
= 160V
V
GS
= 12V, I
D
= 58A
V
GS
= 12V, I
D
= 37A
200
2.0
-
-
-
-
MAX
-
4.5
100
25
1.91
0.031
MIN
200
1.5
4.5
100
50
2.26
0.035
MAX
UNITS
V
V
nA
µA
V
100K RAD
300K RAD
I
SD
= 58A
I
SD
= 58A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
TYP
-
-
4.6
MAX
1.2
375
UNITS
V
ns
µC
Electrical Specifications up to 300K RAD
Single Event Effects (SEB, SEGR)
Note 4
ENVIRONMENT
(NOTE 5)
TEST
Single Event Effects Safe Operating Area
SYMBOL
SEESOA
ION
SPECIES
Br
Br
I
I
Au
Au
NOTES:
4. Testing conducted at Brookhaven National Labs.
5. Fluence = 1E5 ions/cm
2
(typical), T = 25
o
C.
6. Does not exhibit Single Event Burnout (SEB) or Single Event Gate Rupture (SEGR).
TYPICAL LET
(MeV/mg/cm)
37
37
60
60
82
82
TYPICAL
RANGE (µ)
36
36
32
32
28
28
APPLIED
V
GS
BIAS
(V)
-10
-15
-2
-8
0
-5
(NOTE 6)
MAXIMUM
V
DS
BIAS (V)
200
160
200
160
160
120
Performance Curves
Unless Otherwise Specified
LET = 37MeV/mg/cm
2
, RANGE = 36µ
LET = 60MeV/mg/cm
2
, RANGE = 32µ
LET = 82MeV/mg/cm
2
, RANGE = 28µ
240
200
160
120
80
40
0
0
-4
-8
V
GS
(V)
-12
-16
-20
FLUENCE = 1E5 IONS/cm
2
(TYPICAL)
TEMP = 25
o
C
240
LET = 37 BROMINE
200
160
V
DS
(V)
120
80
40
0
0
-5
-10
-15
V
GS
(V)
-20
-25
-30
LET = 82 GOLD
V
DS
(V)
LET = 60 IODINE
FIGURE 1. SINGLE EVENT EFFECTS SAFE OPERATING AREA
FIGURE 2. TYPICAL SEE SIGNATURE CURVE
©2001 Fairchild Semiconductor Corporation
FSPYC260R, FSPYC260F Rev. B
FSPYC260R, FSPYC260F
Performance Curves
1E-3
LIMITING INDUCTANCE (HENRY)
Unless Otherwise Specified
(Continued)
70
60
I
D
, DRAIN (A)
1E-4
ILM = 10A
30A
1E-5
100A
300A
1E-6
50
40
30
20
10
1E-7
10
30
100
DRAIN SUPPLY (V)
300
1000
0
-50
0
50
100
150
T
C
, CASE TEMPERATURE (
o
C)
FIGURE 3. TYPICAL DRAIN INDUCTANCE REQUIRED TO
LIMIT GAMMA DOT CURRENT TO I
AS
500
FIGURE 4. MAXIMUM CONTINUOUS DRAIN CURRENT vs
TEMPERATURE
100
I
D
, DRAIN CURRENT (A)
12V
10
100µs
1ms
1
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
10ms
Q
GS
V
G
Q
GD
Q
G
0.1
1
10
100
500
CHARGE
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING ARE A
FIGURE 6. BASIC GATE CHARGE WAVEFORM
2.5
I
D
, DRAIN TO SOURCE CURRENT (A)
PULSE DURATION = 250ms, V
GS
= 12V, I
D
= 37A
2.0
NORMALIZED r
DS(ON)
200
DESCENDING ORDER
V
GS
= 14V
V
GS
= 12V
V
GS
= 10V
V
GS
= 8V
160
1.5
120
1.0
80
0.5
40
V
GS
= 6V
0
0
2
4
6
8
10
0.0
-80
-40
0
40
80
120
160
T
J
, JUNCTION TEMPERATURE (
o
C)
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TYPICAL NORMALIZED r
DS(ON)
vs JUNCTION
TEMPERATURE
FIGURE 8. TYPICAL OUTPUT CHARACTERISTICS
©2001 Fairchild Semiconductor Corporation
FSPYC260R, FSPYC260F Rev. B
FSPYC260R, FSPYC260F
Performance Curves
NORMALIZED THERMAL RESPONSE (Z
θJC
)
10
Unless Otherwise Specified
(Continued)
1
0.5
0.2
0.1
0.05
0.02
0.01
0.1
SINGLE PULSE
P
DM
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
+ T
C
t
1
10
0
t
2
10
1
0.01
0.001
10
-5
10
-4
10
-3
10
-2
10
-1
t, RECTANGULAR PULSE DURATION (s)
FIGURE 9. NORMALIZED MAXIMUM TRANSIENT THERMAL RESPONSE
300
I
AS
, AVALANCHE CURRENT (A)
100
STARTING T
J
= 25
o
C
STARTING T
J
= 150
o
C
10
IF R = 0
t
AV
= (L) (I
AS
) / (1.3 RATED BV
DSS
- V
DD
)
IF R
0
t
AV
= (L/R) ln [(I
AS
*R) / (1.3 RATED BV
DSS
- V
DD
) + 1]
0.01
0.1
1
10
1
0.001
t
AV
, TIME IN AVALANCHE (ms)
FIGURE 10. UNCLAMPED INDUCTIVE SWITCHING
Test Circuits and Waveforms
ELECTRONIC SWITCH OPENS
WHEN I
AS
IS REACHED
V
DS
L
+
CURRENT I
TRANSFORMER
AS
BV
DSS
t
P
I
AS
50Ω
+
V
DD
V
DS
V
DD
-
VARY t
P
TO OBTAIN
REQUIRED PEAK I
AS
V
GS
20V
-
DUT
50V-150V
50Ω
t
AV
0V
t
P
FIGURE 11. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 12. UNCLAMPED ENERGY WAVEFORMS
©2001 Fairchild Semiconductor Corporation
FSPYC260R, FSPYC260F Rev. B
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参数对比
与FSPYC260R4相近的元器件有:FSPYC260F4、FSPYC260R3。描述及对比如下:
型号 FSPYC260R4 FSPYC260F4 FSPYC260R3
描述 Power Field-Effect Transistor, 58A I(D), 200V, 0.031ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN Power Field-Effect Transistor, 58A I(D), 200V, 0.031ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN Power Field-Effect Transistor, 58A I(D), 200V, 0.031ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, SMD2, 3 PIN
是否无铅 含铅 含铅 含铅
是否Rohs认证 不符合 不符合 不符合
厂商名称 International Rectifier ( Infineon ) International Rectifier ( Infineon ) International Rectifier ( Infineon )
包装说明 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3 CHIP CARRIER, R-CBCC-N3
针数 3 3 3
Reach Compliance Code compliant compliant compliant
ECCN代码 EAR99 EAR99 EAR99
外壳连接 DRAIN DRAIN DRAIN
配置 SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压 200 V 200 V 200 V
最大漏极电流 (ID) 58 A 58 A 58 A
最大漏源导通电阻 0.031 Ω 0.031 Ω 0.031 Ω
FET 技术 METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
JESD-30 代码 R-CBCC-N3 R-CBCC-N3 R-CBCC-N3
JESD-609代码 e0 e0 e0
元件数量 1 1 1
端子数量 3 3 3
工作模式 ENHANCEMENT MODE ENHANCEMENT MODE ENHANCEMENT MODE
最高工作温度 150 °C 150 °C 150 °C
封装主体材料 CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 CHIP CARRIER CHIP CARRIER CHIP CARRIER
峰值回流温度(摄氏度) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
极性/信道类型 N-CHANNEL N-CHANNEL N-CHANNEL
最大脉冲漏极电流 (IDM) 200 A 200 A 200 A
认证状态 Not Qualified Not Qualified Not Qualified
表面贴装 YES YES YES
端子面层 TIN LEAD TIN LEAD TIN LEAD
端子形式 NO LEAD NO LEAD NO LEAD
端子位置 BOTTOM BOTTOM BOTTOM
处于峰值回流温度下的最长时间 NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
晶体管应用 SWITCHING SWITCHING SWITCHING
晶体管元件材料 SILICON SILICON SILICON
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免费申请: 《RT-Thread设备驱动开发指南》来了
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VisualGDB调试F7discovery下载器问题
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lidonglei1 stm32/stm8
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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