GS88037BGT-250V,GS88037BGT-250V pdf中文资料,GS88037BGT-250V引脚图,GS88037BGT-250V电路-Datasheet-电子工程世界

文档预览

GS88037BT-xxxV

100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• Single Cycle Deselect (SCD) operation

• 1.8 V or 2.5 V +10%/–10% core power supply

• 1.8 V or 2.5 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

256K x 36

9Mb Sync Burst SRAM

250 MHz–200 MHz

1.8 V or 2.5 V V

1.8 V or 2.5 V I/O

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

SCD Pipelined Reads

The GS88037BT-xxxV is a SCD (Single Cycle Deselect)

pipelined synchronous SRAM. DCD (Dual Cycle Deselect)

versions are also available. SCD SRAMs pipeline deselect

commands one stage less than read commands. SCD RAMs

begin turning off their outputs immediately after the deselect

command has been captured in the input registers.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS88037BT-xxxV operates on a 1.8 V or 2.5 V power

supply. All input are 2.5 V and 1.8 V compatible. Separate

output power (V

DDQ

) pins are used to decouple output noise

from the internal circuits and are 2.5 V and 1.8 V compatible.

Functional Description

Applications

The GS88037BT-xxxV is a 9,437,184-bit (8,388,608-bit for

x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

cycles can be initiated with either ADSP or ADSC inputs. In

Parameter Synopsis

Pipeline

3-1-1-1

tCycle

Curr

(x36)

-250

2.5

4.0

330

-200

2.5

5.0

270

Unit

Rev: 1.03 6/2006

1/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88037BT-xxxV

GS88037BT-xxxV 100-Pin TQFP Pinout

DQP

DDQ

/DNU

DDQ

DQP

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

256K x 36

Top View

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

ADSC

ADSP

ADV

DQP

DDQ

DQP

Rev: 1.03 6/2006

LBO

2/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88037BT-xxxV

TQFP Pin Description

Symbol

, A

, B

, E

ADV

ADSP, ADSC

LBO

DDQ

/DNU

Type

Description

Address field LSBs and Address Counter preset Inputs

Address Inputs

I/O

Data Input and Output pins

—

No Connect

Byte Write—Writes all enabled bytes; active low

Byte Write Enable for DQ

, DQ

Data I/Os; active low

Byte Write Enable for DQ

, DQ

Data I/Os; active low

Clock Input Signal; active high

Global Write Enable—Writes all bytes; active low

Chip Enable; active low

Chip Enable; active high

Output Enable; active low

Burst address counter advance enable; active low

Address Strobe (Processor, Cache Controller); active low

Sleep Mode control; active high

Linear Burst Order mode; active low

Core power supply

I/O and Core Ground

Output driver power supply

DDQ

or V

(must be tied high)

Do Not Use (must be left floating)

Rev: 1.03 6/2006

3/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88037BT-xxxV

GS88037BT-xxxV Block Diagram

–

Counter

Load

LBO

ADV

ADSC

ADSP

Memory

Array

Power Down

Control

SCD=1

DQx1

–

DQx9

Note: Only x36 version shown for simplicity.

Rev: 1.03 6/2006

4/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

GS88037BT-xxxV

Mode Pin Functions

Mode Name

Burst Order Control

Power Down Control

Pin Name

LBO

State

L or NC

Function

Linear Burst

Interleaved Burst

Active

Standby, I

= I

Note:

There is a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the

above table.

Burst Counter Sequences

Linear Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

Interleaved Burst Sequence

A[1:0] A[1:0] A[1:0] A[1:0]

1st address

2nd address

3rd address

4th address

Note:

The burst counter wraps to initial state on the 5th clock.

Note:

The burst counter wraps to initial state on the 5th clock.

BPR 1999.05.18

Rev: 1.03 6/2006

5/19

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

参数对比

与GS88037BGT-250V相近的元器件有：GS88037BT-200V、GS88037BT-250IV、GS88037BT-250V、GS88037BT-V、GS88037BT-200IV、GS88037BGT-250IV、GS88037BGT-200V、GS88037BGT-200IV。描述及对比如下：

型号	GS88037BGT-250V	GS88037BT-200V	GS88037BT-250IV	GS88037BT-250V	GS88037BT-V	GS88037BT-200IV	GS88037BGT-250IV	GS88037BGT-200V	GS88037BGT-200IV
描述	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM	256K x 36 9Mb Sync Burst SRAM
是否Rohs认证	符合	不符合	不符合	不符合	-	不符合	符合	符合	符合
厂商名称	GSI Technology	GSI Technology	GSI Technology	GSI Technology	-	GSI Technology	GSI Technology	GSI Technology	GSI Technology
零件包装代码	QFP	QFP	QFP	QFP	-	QFP	QFP	QFP	QFP
包装说明	LQFP,	LQFP,	LQFP,	LQFP,	-	LQFP,	LQFP,	LQFP,	LQFP,
针数	100	100	100	100	-	100	100	100	100
Reach Compliance Code	unknown	unknown	unknown	unknown	-	unknown	unknown	unknown	unknown
ECCN代码	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	-	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B	3A991.B.2.B
最长访问时间	2.5 ns	2.5 ns	2.5 ns	2.5 ns	-	2.5 ns	2.5 ns	2.5 ns	2.5 ns
其他特性	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	-	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY	PIPELINED ARCHITECTURE; ALSO OPERATES AT 2.5V SUPPLY
JESD-30 代码	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	-	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100	R-PQFP-G100
长度	20 mm	20 mm	20 mm	20 mm	-	20 mm	20 mm	20 mm	20 mm
内存密度	9437184 bit	9437184 bit	9437184 bit	9437184 bit	-	9437184 bit	9437184 bit	9437184 bit	9437184 bit
内存集成电路类型	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM	-	CACHE SRAM	CACHE SRAM	CACHE SRAM	CACHE SRAM
内存宽度	36	36	36	36	-	36	36	36	36
功能数量	1	1	1	1	-	1	1	1	1
端子数量	100	100	100	100	-	100	100	100	100
字数	262144 words	262144 words	262144 words	262144 words	-	262144 words	262144 words	262144 words	262144 words
字数代码	256000	256000	256000	256000	-	256000	256000	256000	256000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	-	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	85 °C	70 °C	-	85 °C	85 °C	70 °C	85 °C
组织	256KX36	256KX36	256KX36	256KX36	-	256KX36	256KX36	256KX36	256KX36
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LQFP	LQFP	LQFP	LQFP	-	LQFP	LQFP	LQFP	LQFP
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	-	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE	FLATPACK, LOW PROFILE
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	-	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	260	260	260
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified
座面最大高度	1.6 mm	1.6 mm	1.6 mm	1.6 mm	-	1.6 mm	1.6 mm	1.6 mm	1.6 mm
最大供电电压 (Vsup)	2 V	2 V	2 V	2 V	-	2 V	2 V	2 V	2 V
最小供电电压 (Vsup)	1.7 V	1.7 V	1.7 V	1.7 V	-	1.7 V	1.7 V	1.7 V	1.7 V
标称供电电压 (Vsup)	1.8 V	1.8 V	1.8 V	1.8 V	-	1.8 V	1.8 V	1.8 V	1.8 V
表面贴装	YES	YES	YES	YES	-	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	INDUSTRIAL	COMMERCIAL	-	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	INDUSTRIAL
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	-	GULL WING	GULL WING	GULL WING	GULL WING
端子节距	0.65 mm	0.65 mm	0.65 mm	0.65 mm	-	0.65 mm	0.65 mm	0.65 mm	0.65 mm
端子位置	QUAD	QUAD	QUAD	QUAD	-	QUAD	QUAD	QUAD	QUAD
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	14 mm	14 mm	14 mm	14 mm	-	14 mm	14 mm	14 mm	14 mm