H8S/2655 Series
H8S/2655
HD6432655, HD6472655,
H8S/2653
HD6432653
Hardware Manual
ADE-602-094C
Rev. 4.0
11/12/98
Hitachi, Ltd.
MC-Setsu
Cautions
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have received the latest product standards or specifications before final design, purchase or use.
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However, contact Hitachi’s sales office before using the product in an application that demands
especially high quality and reliability or where its failure or malfunction may directly threaten
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support.
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particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider
normally foreseeable failure rates or failure modes in semiconductor devices and employ
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Preface
The H8S/2655 Series is a series of high-performance microcontrollers with a 32-bit H8S/2600
CPU core, and a set of on-chip supporting functions required for system configuration.
The H8S/2600 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit
general registers with a 32-bit internal configuration, and a concise and optimized instruction set.
The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based
on the high-level language C can also be run efficiently.
The address space is divided into eight areas. The data bus width and access states can be selected
for each of these areas, and various kinds of memory can be connected fast and easily.
On-chip memory consists of large-capacity ROM and RAM. PROM (ZTAT™*) and mask ROM
versions are available, providing a quick and flexible response to conditions from ramp-up through
full-scale volume production, even for applications with frequently changing specifications.
On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse
generator (PPG), 8-bit timers, watchdog timer (WDT), serial communication interface (SCI), A/D
converter, D/A converter, and I/O ports.
In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided,
enabling high-speed data transfer without CPU intervention.
Use of the H8S/2655 Series enables compact, high-performance systems to be implemented easily.
This manual describes the hardware of the H8S/2655 Series. Refer to the H8S/2600 Series and
H8S/2000 Series Programming Manual for a detailed description of the instruction set.
Note: * ZTAT is a trademark of Hitachi, Ltd.
Main Revisions and Additions in This Edition
Page
144
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Section
Revision Contents
6.2.6. Memory Control Register (MCR): description of Bit 5 Description amendments
Figure 6-14 Example of Wait State Insertion Timing
Figure 6-47 Bus-Released State Transition Timing
Table 7-9 Register Functions in Single Address Mode
7.5.8 DMAC Activation Sources
Single Address Mode
10.2.1 Timer Control Register (TCR)
10.2.2 Timer Mode Register (TMDR)
10.2.3 Timer I/O Control Register (TIOR)
10.2.8 Timer Start Register (TSTR)
10.7 Usage Notes: Contention between TCNT Write and
Overflow/Underflow
10.7 Usage Notes: Interrupts and Module Stop Mode
14.2.9 Smart Card Mode Register (SCMR): description of
Bit 3
Figure 14-15 Sample SCI Initialization Flowchart
Figure 14-20 Sample Flowchart of Simultaneous Serial
Transmit and Receive Operations
15.2.3 Serial Mode Register (SMR): description of Bit 7
15.2.4 Serial Control Register (SCR)
Figure amended
Figure amended
Table amendments
Description amendments
Description amendments
Descriptive text added
Note amended
Description amendments
Descriptive text added
addition
Descriptive text added
Note added
Note amended
Amended
Amended
19.2.1 Bus Control Register L (BCRL): description of Bits 4 Added
and 3
Figure 19-2 Wiring of Socket Adapter
Figure amended
Table amendments
Note deleted
802 to 804 Table A.1 Instruction Set
1005
1006
1007
1008
1009
1010
1011
1026
Figure C-1 (a) Port1 Block Diagram (Pins P1
0
and P1
1
)
Figure C-1 (b) Port1 Block Diagram (Pins P1
2
, P1
3
, P1
5
, and Note deleted
P1
7
)
Figure C-1 (c) Port1 Block Diagram (Pins P1
4
and P1
6
)
Figure C-2 (a) Port2 Block Diagram (Pins P2
0
and P2
1
)
Figure C-2 (b) Port2 Block Diagram (Pins P2
2
and P2
4
)
Figure C-2 (c) Port2 Block Diagram (Pins P2
3
and P2
5
)
Figure C-2 (d) Port2 Block Diagram (Pins P2
6
and P2
7
)
Figure C-7 (a) PortA Block Diagram (Pins PA
0
to PA
3
)
Note deleted
Note deleted
Note deleted
Note deleted
Note deleted
Figure amended
