March 2008
HYS64T64020EM–2.5–B2
HYS64T64020EM–[3/3S]–B2
HYS64T64020EM–3.7–B2
HYB64T64020EM–5–B2
214-Pin Unbuffered DDR2 SDRAM MicroDIMM Modules
MDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.10
Internet Data Sheet
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
Unbuffered DDR2 SDRAM MicroDIMM Modules
HYS64T64020EM–2.5–B2, HYS64T64020EM–[3/3S]–B2, HYS64T64020EM–3.7–B2, HYB64T64020EM–5–B2
Revision History: 2008-03, Rev. 1.10
Page
All
All
All
Subjects (major changes since last revision)
Added Product type HYS64T64020EM-2.5-B2 and adapted to internet edition.
Technical Change and updated to final version of document.
Preliminary Copy
Previous revision 1.0, 2007-09
Previous revision 0.50, 2007-04
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qag_techdoc_A4, 4.20, 2008-01-25
09032007-YO3V-5RUJ
2
Internet Data Sheet
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
Unbuffered DDR2 SDRAM MicroDIMM Modules
1
Overview
This chapter gives an overview of the 214-pin Micro-DIMM DDR2 SDRAM modules product family and describes its main
characteristics.
1.1
Features
•
•
•
•
•
•
•
•
•
•
•
Auto Refresh for temperatures above 85 °C
t
REFI
= 3.9
µs.
Programmable self refresh rate via EMRS2 setting.
Programmable partial array refresh via EMRS2 settings.
DCC enabling via EMRS2 setting.
All inputs and outputs SSTL_1.8 compatible.
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT).
2-piece type Mezzanine Socket with 0,4 mm contact
centers.
Serial Presence Detect with E
2
PROM.
MDIMM Dimensions (nominal): 30 mm high, 54 mm wide
Based on standard reference layouts Raw Cards 'A'.
RoHS compliant products
1)
.
• 214-Pin PC2-6400, PC2-5300, PC2-4200 and PC2-3200
DDR2 SDRAM memory modules.
• Two 64M
×
64 module organization, and 32M
×
16 chip
organization.
• 512MB Modules built with 512Mbit DDR2 SDRAMs in
chipsize packages PG-TFBGA-84.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply.
• All speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Programmable CAS Latencies (3, 4, 5 ), Burst Length (8 &
4).
• Auto Refresh (CBR) and Self Refresh.
TABLE 1
Performance Table
QAG Speed Code
DRAM Speed Grade
Module Speed Grade
CAS-RCD-RP latencies
Max.
Clock Frequency
CL3
CL4
CL5
CL6
DDR2
PC2
–2.5
–800E
–6400E
6–6–6
200
266
333
400
15
15
45
40
15
–3
–667C
–5300C
4–4–4
200
333
333
–
12
12
45
40
12
–3S
–667D
–5300D
5–5–5
200
266
333
–
15
15
45
40
15
–3.7
–533C
–4200C
4–4–4
200
266
266
–
15
15
45
40
15
–5
–400B
–3200B
3–3–3
200
200
–
–
15
15
40
40
15
Unit
t
CK
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
1)
Min. Row Active Time
2)
Precharge-All (4 banks)
command period
f
CK3
f
CK4
f
CK5
f
CK6
t
RCD
t
RP
t
RAS
t
RAS
t
PREA
1) Product released after 2007-08-01 will support
t
RAS
= 40 ns for all DDR2 speed sort.
2) For products released after 2007-08-01.
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.10, 2008-03
09032007-YO3V-5RUJ
3
Internet Data Sheet
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
Unbuffered DDR2 SDRAM MicroDIMM Modules
1.2
Description
The memory array is designed with 512MBit Double-Data-
Rate-Two (DDR2) Synchronous DRAMs.
Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E
2
PROM
device using the 2-pin I
2
C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
The
Qimonda
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
module family are Micro-DIMM modules “MDIMMs” with 30
mm height based on DDR2 technology.
DIMMs
are
available
as
non-ECC
modules
in64M
×
64 (512MB) in organization and density, intended for
mounting into 214-pin connector sockets.
TABLE 2
Ordering Information
Product Type
1)
PC2-6400 (6-6-6)
HYS64T64020EM-2.5-B2
PC2-5300 (4-4-4)
HYS64T64020EM-3-B2
PC2-5300 (5-5-5)
HYS64T64020EM-3S-B2
PC2-4200 (4-4-4)
HYS64T64020EM-3.7-B2
PC2-3200 (3-3-3)
HYS64T64020EM-5-B2
512MB 2R×16 PC2–3200M–333–12–A0
2 Ranks, Non-ECC
512Mbit (×16)
1) For detailed information regarding Product Type of Qimonda please see chapter "Product Type Nomenclature" of this datasheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example "PC2–6400M–666–12–A0" where
6400M means Micro-DIMM modules with 6.40 GB/sec Module Bandwidth and "666–12" means Column Address Strobe (CAS) latency
=6, Row Column Delay (RCD) latency = 6 and Row Precharge (RP) latency = 6 using the JEDEC SPD Revision 1.2 and produced on the
Raw Card "A".
Compliance Code
2)
512MB 2R×16 PC2–6400M–666–12–A0
512MB 2R×16 PC2–5300M–444–12–A0
512MB 2R×16 PC2–5300M–555–12–A0
512MB 2R×16 PC2–4200M–444–12–A0
Description
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
2 Ranks, Non-ECC
SDRAM Technology
512Mbit (×16)
512Mbit (×16)
512Mbit (×16)
512Mbit (×16)
TABLE 3
Address Format
DIMM
Density
512MB
Module
Organization
64M
×
64
Memory
Ranks
2
ECC/
Non-ECC
Non-ECC
# of SDRAMs # of row/bank/column
bits
8
13/2/10
Raw
Card
A
TABLE 4
Components on Modules
Product Type
1)2)
HYS64T64020EM
DRAM Components
1)
HYB18T512160B2F
DRAM Density
512Mbit
DRAM Organisation
32M
×
16
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.10, 2008-03
09032007-YO3V-5RUJ
4
Internet Data Sheet
HYS64T64020EM–[2.5/3/3S/3.7/5]–B2
Unbuffered DDR2 SDRAM MicroDIMM Modules
2
2.1
Pin Configurations
Pin Configurations
The pin configuration of the DDR2 SDRAM Micro-DIMM is listed by function in
Table 5
(214 pins). The abbreviations used in
columns Pin and Buffer Type are explained in
Table 6
and
Table 7
respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of MDIMM
Ball No.
Clock Signals
122
194
123
195
43
147
CK0
CK1
CK0
CK1
CKE0
CKE1
I
I
I
I
I
I
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Clock Signal CK 1:0, Complementary Clock Signal CK 1:0
Note: The system clock inputs. All address and command lines are
sampled on the cross point of the rising edge of CK and the falling
edge of CK. A Delay Locked Loop (DLL) circuit is driven from the
clock inputs and output timing for read operations is synchronized
to the input clock.
Clock Enables 1:0
Notes:
1. Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
2. 2-rank module
NC
Control Signals
165
62
S0
S1
I
I
SSTL
SSTL
Chip Select Rank 1:0
Notes:
1. Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue. Rank 0 is selected by S0; Rank 1 is selected by
S1.
2. 2-rank module
NC
NC
Not Connected
Note: 1-rank module
NC
Not Connected
Note: 1-rank module
Name
Pin
Type
Buffer
Type
Function
Rev. 1.10, 2008-03
09032007-YO3V-5RUJ
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