IBM0316169CT3D-80,IBM0316169CT3D-80 pdf中文资料,IBM0316169CT3D-80引脚图,IBM0316169CT3D-80电路-Datasheet-电子工程世界

文档预览

Discontinued (12/98 - last order; 9/99 last ship)

IBM0316409C

IBM0316169C

IBM03164B9C

16Mb Synchronous DRAM-Die Revision D

IBM0316809C

Features

• High Performance:

-80

CL=3

-360

CL=3

-10

CL=3

• Multiple Burst Read with Single Write Option

Units

MHz

• Automatic and Controlled Precharge Command

• Data Mask for Read/Write control (x4, x8)

• Dual Data Mask for byte control (x16)

• Auto Refresh (CBR), Self Refresh (SR)

Clock Frequency

Clock Cycle

Clock Access Time

125

100

5.5

100

• Suspend Mode and Power Down Mode

• Single Pulsed RAS Interface

• Fully Synchronous to Positive Clock Edge

• Dual Banks controlled by A11 (Bank Select)

• Programmable CAS Latency: 1,2,3

• Programmable Burst Length: 1,2,4,8,full-page

• Programmable Wrap Sequence: Sequential or

Interleave

• 4096 refresh cycles/64ms

• Random Column Address every CLK (1-N Rule)

• Single 3.3V

0.3V Power Supply

• Supports LVTTL I/O interface

• Package: 44 pin 400 mil TSOP-Type II (x4,x8)

50 pin 400 mil TSOP-Type II (x16)

2-High Stack TSOJ

Description

IBM’s 0316409C, 0316809C, and 0316169C

are dual bank Synchronous DRAMs organized as

2Mbit x 4 I/O x 2 Bank, 1Mbit x 8 I/O x 2 Bank, and

512Kbit x 16 I/O x 2 Bank, respectively. These

devices support LVTTL I/O interface levels.

stacked version of the x 4 component is also

offered. These synchronous devices achieve high

speed data transfer rates of up to 125 MHz. The

chip is fabricated with IBM’s advanced 16Mbit

CMOS DRAM process technology.

The device is designed to comply with all

JEDEC standards set for synchronous DRAM prod-

ucts, both electrically and mechanically. All of the

control, address and data input/output circuits are

synchronized with the positive edge of an externally

supplied clock (CLK).

Internal chip operating modes are defined by

combinations of RAS, CAS, WE, and CS and a com-

mand decoder initiates the necessary timings for

each operation. A twelve bit address bus accepts

address data in the conventional RAS/CAS multi-

plexing style. Eleven row addresses (A0-A10) and a

bank select address (A11) are strobed with RAS.

Ten column addresses (A0-A9) plus A10 and a bank

select address (A11) are strobed with CAS. Column

08J3348.E35853

5/98

address A9 is dropped on the x8 device and column

addresses A8 and A9 are dropped on the x16

device. Access to the lower or upper DRAM in a

stacked device is controlled by CS0 and CS1.

Prior to any access operation, the CAS latency,

burst length, and burst sequence must be pro-

grammed into the device by address inputs A0-A11

during a mode register set cycle. In addition, it is

possible to program a multiple burst sequence with

single write cycle for write through cache operation.

Operating the two memory banks in an inter-

leave fashion allows random access operation to

occur at a higher rate than is possible with standard

DRAMs. A sequential and gapless data rate of up to

125 MHz is possible depending on burst length,

CAS latency, and speed grade of the device.

Auto Refresh (CBR) and Self Refresh (SR)

operation are supported. Refreshing both decks of a

stacked device simultaneously is allowed during

Self Refresh but all other stacked device operations

must be performed on a single deck at a time.

Use is further subject to the provisions at the end of this document.

Page 1 of 120

Discontinued (12/98 - last order; 9/99 last ship)

IBM0316409C IBM0316809C IBM0316169C

IBM03164B9C

16Mb Synchronous DRAM-Die Revision D

Pin Assignments for Planar Components

(Top View)

VDD

VSSQ

DQ0

VDDQ

VSSQ

DQ1

VDDQ

CAS

RAS

A11(BS)

A10

VDD

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

DQM

CLK

CKE

VDD

DQ0

VSSQ

DQ1

VDDQ

DQ2

VSSQ

DQ3

VDDQ

CAS

RAS

A11(BS)

A10

VDD

DQ7

VSSQ

DQ6

VDDQ

DQ5

VSSQ

DQ4

VDDQ

DQM

CLK

CKE

VDD

DQ0

DQ1

VSSQ

DQ2

DQ3

VDDQ

DQ4

DQ5

VSSQ

DQ6

DQ7

VDDQ

LDQM

CAS

RAS

A11(BS)

A10

VDD

DQ15

DQ14

VSSQ

DQ13

DQ12

VDDQ

DQ11

DQ10

VSSQ

DQ9

DQ8

VDDQ

UDQM

CLK

CKE

44-pin Plastic TSOP(II) 400 mil

2Mbit x 4 I/O x 2 Bank

IBM0316409CT3

44-pin Plastic TSOP(II) 400 mil

1Mbit x 8 I/O x 2 Bank

IBM0316809CT3

50-pin Plastic TSOP(II) 400 mil

512Kbit x 16 I/O x 2 Bank

IBM0316169CT3

Pin Description

CLK

CKE

RAS

CAS

A11 (BS)

A0 - A10

Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Bank Select

Address Inputs

DQ0-DQ15

DQM, LDQM, UDQM

VDD

VSS

VDDQ

VSSQ

—

Data Input/Output

Data Mask

Power (+3.3V)

Ground

Power for DQs (+3.3V)

Ground for DQs

No Connection

—

Use is further subject to the provisions at the end of this document.

08J3348.E35853

5/98

Page 2 of 120

Discontinued (12/98 - last order; 9/99 last ship)

IBM0316409C

IBM0316169C

IBM03164B9C

16Mb Synchronous DRAM-Die Revision D

IBM0316809C

Pin Assignments for 2-High Stack Package (Dual CS Pins)

(Top View)

VDD

VSSQ

DQ0

VDDQ

VSSQ

DQ1

VDDQ

CAS

RAS

* CS0/NC

A11 (BS)

A10

VDD

VSSQ

DQ3

VDDQ

VSSQ

DQ2

VDDQ

DQM

CLK

CKE

NC/CS1 *

44-pin Plastic TSOJ(II) 400 mil

(2Mbit x 4 I/O x 2 Bank) x 2 High

IBM03164B9CT3

* CS0 selects the lower DRAM in the stack.

* CS1 selects the upper DRAM in the stack.

Pin Description

CLK

CKE

CS0, CS1

RAS

CAS

A11 (BS)

A0 - A10

Clock Input

Clock Enable

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

Bank Select

Address Inputs

DQ0-DQ3

DQM

VDD

VSS

VDDQ

VSSQ

—

Data Input/Output

Data Mask

Power (+3.3V)

Ground

Power for DQs (+3.3V)

Ground for DQs

No Connection

—

08J3348.E35853

5/98

Use is further subject to the provisions at the end of this document.

Page 3 of 120

Discontinued (12/98 - last order; 9/99 last ship)

IBM0316409C IBM0316809C IBM0316169C

IBM03164B9C

16Mb Synchronous DRAM-Die Revision D

Input/Output Functional Description

Symbol

CLK

Type

Input

Signal

Pulse

Polarity

Positive

Edge

Active

High

Function

The system clock input. All of the SDRAM inputs are sampled on the rising edge of the

clock.

Activates the CLK signal when high and deactivates the CLK signal when low. By deacti-

vating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self

Refresh mode.

CKE

Input

Level

CS,

CS0, CS1

RAS, CAS

A11 (BS)

Input

Pulse

CS (CS0, CS1 for stacked devices) enables the command decoder when low and disables

Active Low the command decoder when high. When the command decoder is disabled, new com-

mands are ignored but previous operations continue.

Active Low

—

When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the

operation to be executed by the SDRAM.

Selects which bank is to be active. A11 low selects bank A and A11 high selects bank B.

During a Bank Activate command cycle, A0-A10 defines the row address (RA0-RA10)

when sampled at the rising clock edge.

During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)

when sampled at the rising clock edge.

Input

Pulse

Level

A0 - A10

Input

Level

—

A10 is used to invoke Auto-Precharge operation. If A10 is high, Auto-Precharge is

selected and A11 defines the bank to be precharged (low=bank A, high=bank B). If A10 is

low, Auto-Precharge is disabled.

During a Precharge command cycle, A10 is used in conjunction with A11 to control which

bank(s) to precharge. If A10 is high, both bank A and bank B will be precharged regardless

of the state of A11. If A10 is low, then A11 is used to define which bank to precharge.

DQ0 - DQ15

DQM

LDQM

UDQM

Input

Output

Level

—

Data Input/Output pins operate in the same manner as on conventional DRAMs.

Input

Pulse

The DQ mask (DQM) places the DQ buffers in a high impedance state when sampled

high. In Read mode, DQM has a latency of two clock cycles and controls the output buffers

Active Low consistent with an output enable. In Write mode, DQM has a latency of zero and operates

as a word mask by allowing input data to be written if it is low but blocks the write opera-

tion if DQM is high.

—

Power and ground for the input buffers and the core logic.

Isolated power supply and ground for the output buffers to provide improved noise immu-

nity.

VDD, VSS

Supply

—

VDDQ, VSSQ Supply

Use is further subject to the provisions at the end of this document.

08J3348.E35853

5/98

Page 4 of 120

Discontinued (12/98 - last order; 9/99 last ship)

IBM0316409C

IBM0316169C

IBM03164B9C

16Mb Synchronous DRAM-Die Revision D

IBM0316809C

Ordering Information - Planar Devices (Single CS Pin)

Part Number

IBM0316409CT3D-80

IBM0316409CT3D-10

IBM0316809CT3D-80

IBM0316809CT3D-360

IBM0316809CT3D-10

IBM0316169CT3D-80

IBM0316169CT3D-10

CAS

Latencies

2,3

1,2,3

2,3

1,2,3

2,3

1,2,3

I/O

Width

x16

I/O

Type

LVTTL

Package

400mil Type II TSOP-44

400mil Type II TSOP-50

Power

Supply

3.3V

Clock

Cycle

8ns

10ns

8ns

10ns

8ns

10ns

Ordering Information - 2 High Stacked Devices (Dual CS Pins)

Part Number

IBM03164B9CT3D-10

CAS

Latencies

1,2,3

I/O

Width

I/O

Type

LVTTL

Package

400mil Type II TSOJ-44 2-High

Power

Supply

3.3V

Clock

Cycle

10ns

08J3348.E35853

5/98

Use is further subject to the provisions at the end of this document.

Page 5 of 120

参数对比

与IBM0316169CT3D-80相近的元器件有：IBM0316409CT3D-10、IBM0316409CT3D-80、IBM0316809CT3D-80、IBM03164B9CT3D-10、IBM0316809CT3D-10、IBM0316169CT3D-10、IBM0316809CT3D-360。描述及对比如下：

型号	IBM0316169CT3D-80	IBM0316409CT3D-10	IBM0316409CT3D-80	IBM0316809CT3D-80	IBM03164B9CT3D-10	IBM0316809CT3D-10	IBM0316169CT3D-10	IBM0316809CT3D-360
描述	Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50	Synchronous DRAM, 4MX4, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44	Synchronous DRAM, 4MX4, 6ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44	Synchronous DRAM, 2MX8, 6ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44	Synchronous DRAM Module, 4MX4, 8ns, CMOS, PDSO44, 0.400 INCH, 2 HIGH STACK, PLASTIC, TSOJ2-44	Synchronous DRAM, 2MX8, 8ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44	Synchronous DRAM, 1MX16, 8ns, CMOS, PDSO50, 0.400 INCH, PLASTIC, TSOP2-50	Synchronous DRAM, 2MX8, 5.5ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44
是否Rohs认证	不符合	不符合	不符合	不符合	不符合	不符合	不符合	不符合
零件包装代码	TSOP2	TSOP2	TSOP2	TSOP2	SOJ	TSOP2	TSOP2	TSOP2
包装说明	TSOP2, TSOP50,.46,32	TSOP2, TSOP44,.46,32	TSOP2, TSOP44,.46,32	TSOP2, TSOP44,.46,32	SOJ, SOJ44,.44,32	TSOP2, TSOP44,.46,32	TSOP2, TSOP50,.46,32	TSOP2, TSOP44,.46,32
针数	50	44	44	44	44	44	50	44
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST
最长访问时间	6 ns	8 ns	6 ns	6 ns	8 ns	8 ns	8 ns	5.5 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	125 MHz	100 MHz	125 MHz	125 MHz	100 MHz	100 MHz	100 MHz	100 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	R-PDSO-G50	R-PDSO-G44	R-PDSO-G44	R-PDSO-G44	R-PDSO-J44	R-PDSO-G44	R-PDSO-G50	R-PDSO-G44
JESD-609代码	e0	e0	e0	e0	e0	e0	e0	e0
长度	20.95 mm	18.41 mm	18.41 mm	18.41 mm	18.4 mm	18.41 mm	20.95 mm	18.41 mm
内存密度	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit	16777216 bit
内存集成电路类型	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
内存宽度	16	4	4	8	4	8	16	8
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	50	44	44	44	44	44	50	44
字数	1048576 words	4194304 words	4194304 words	2097152 words	4194304 words	2097152 words	1048576 words	2097152 words
字数代码	1000000	4000000	4000000	2000000	4000000	2000000	1000000	2000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	1MX16	4MX4	4MX4	2MX8	4MX4	2MX8	1MX16	2MX8
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	TSOP2	TSOP2	TSOP2	TSOP2	SOJ	TSOP2	TSOP2	TSOP2
封装等效代码	TSOP50,.46,32	TSOP44,.46,32	TSOP44,.46,32	TSOP44,.46,32	SOJ44,.44,32	TSOP44,.46,32	TSOP50,.46,32	TSOP44,.46,32
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
电源	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096	4096	4096	4096
座面最大高度	1.2 mm	1.2 mm	1.2 mm	1.2 mm	3.2 mm	1.2 mm	1.2 mm	1.2 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
最大待机电流	0.002 A	0.002 A	0.002 A	0.002 A	0.004 A	0.002 A	0.002 A	0.002 A
最大压摆率	0.24 mA	0.175 mA	0.22 mA	0.22 mA	0.175 mA	0.175 mA	0.19 mA	0.175 mA
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子面层	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
端子形式	GULL WING	GULL WING	GULL WING	GULL WING	J BEND	GULL WING	GULL WING	GULL WING
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
处于峰值回流温度下的最长时间	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED
宽度	10.16 mm	10.16 mm	10.16 mm	10.16 mm	10.15 mm	10.16 mm	10.16 mm	10.16 mm
厂商名称	IBM	-	IBM	IBM	IBM	IBM	IBM	IBM
交错的突发长度	1,2,4,8	1,2,4,8	1,2,4,8	1,2,4,8	-	1,2,4,8	1,2,4,8	1,2,4,8
连续突发长度	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP	-	1,2,4,8,FP	1,2,4,8,FP	1,2,4,8,FP