ICS7151A-50
Spread Spectrum Clock Generator
Description
The ICS7151A-50 is a clock generator for EMI
(Electromagnetic Interference) reduction. Spectral
peaks are attenuated by modulating the system clock
frequency. Down or center spread profiles are
selectable. Down spread will not exceed the maximum
frequency of an unspread clock, and center spread
does not change the average operating frequency of
the system
ICS offers many other clocks for computers and
computer peripherals. Consult ICS when you need to
remove crystals and oscillators from your board.
Features
•
•
•
•
•
•
Operating voltage of 3.3 V ±0.3 V
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Input frequency range of 16.5 to 33.4 MHz
Output frequency ranges of 8.3 to 16.7 MHz
Provides a spread spectrum clock output (±0.5%,
±1.5% center spread; -1.0%, -3.0% down spread)
•
Multiplication rate of x1/2
•
Advanced, low-power CMOS process
•
Pin compatible with the Fujitsu MB88151-500
Block Diagram
VDD
S1:0
2
ENS
PLL Clock
Synthesis
and Spread
Spectrum
Circuitry
Clock Buffer/
Crystal
Ocsillator
CKOUT
XIN
XOUT
External caps required with crystal for
accurate tuning of the clock
GND
MDS 7151A-50 A
Integrated Circuit Systems, Inc.
●
1
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
ICS7151A-50
Spread Spectrum Clock Generator
Pin Assignment
XIN
GND
S0
S1
1
2
3
4
8
7
6
5
8 pin (150 mil) SOIC
XOUT
VDD
ENS
CKOUT
Spread Direction and Percentage
Select Table
S1
Pin 4
0
0
1
1
ENS
(note 1)
S0
Pin 3
0
1
0
1
Spread
Direction
Center
Center
Down
Down
Modulation
No Modulation
Modulation
Spread
Percentage (%)
±1.5
±0.5
-1.0
-3.0
0
1
Notes:
1. Pin 1 has a pull-up resistor.
Pin Descriptions
Pin
Number
Pin
Name
Pin Type
Pin Description
1
2
3
4
5
6
7
8
XIN
GND
S0
S1
CKOUT
ENS
VDD
XOUT
Input
Power
Input
Input
Output
Input
Power
Output
Crystal pin/clock input pin.
Connect to ground.
Select pin 0. Spread modulation select.
Select pin 1. Spread modulation select.
Clock output.
Modulation enable. Internal pull-up resistor.
Connect to +3.3 V.
Crystal connection pin.
MDS 7151A-50 A
Integrated Circuit Systems, Inc.
●
2
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
ICS7151A-50
Spread Spectrum Clock Generator
External Components
The ICS7151A-50 requires a minimum number of
external components for proper operation.
traces just underneath the device, or on layers adjacent
to the ground plane layer used by the device.
Crystal Information
The crystal used should be a fundamental mode (do
not use third overtone), parallel resonant. Crystal
capacitors should be connected from pins X1 to ground
and X2 to ground to optimize the initial accuracy. The
value of these capacitors is given by the following
equation:
Crystal caps (pF) = (C
L
- 6) x 2
In the equation, C
L
is the crystal load capacitance. So,
for a crystal with a 16 pF load capacitance, two 20 pF
[(16-6) x 2] capacitors should be used.
Decoupling Capacitor
A decoupling capacitor of 0.01µF must be connected
between GND and VDD on pins 2 and 7, as close to
these pins as possible. For optimum device
performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the
use of vias in the decoupling circuit.
Series Termination Resistor
Series termination should be used on the clock output.
To series terminate a 50Ω trace (a commonly used
trace impedance) place a 27Ω resistor in series with
the clock line, as close to the clock output pin as
possible. The nominal impedance of the clock output is
25Ω.
Spread Spectrum Profile
The ICS7151A-50 low EMI clock generator uses a
triangular frequency modulation profile for optimal
down stream tracking of zero delay buffers and other
PLL devices. The frequency modulation amplitude is
constant with variations of the input frequency.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) The 0.01µF decoupling capacitor should be mounted
on the component side of the board as close to the
VDD pin as possible. No vias should be used between
the decoupling capacitor and VDD pin. The PCB trace
to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) To minimize EMI, the 27Ω series termination resistor
(if needed) should be placed close to the clock output.
3) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS7151A-50. This includes signal
Modulation Rate
Frequency
Time
MDS 7151A-50 A
Integrated Circuit Systems, Inc.
●
3
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
ICS7151A-50
Spread Spectrum Clock Generator
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS7151A-50. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs (referenced to GND)
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
Overshoot (V
IOVER
)
Undershoot (V
IUNDER
)
-0.5 to 4.0 V
Rating
-0.5 V to VDD+0.5 V
-40 to +85°C
-55 to +125°C
-40 to +125°C
260°C
VDD + 1.0 V (t
OVER
< 50 ns)
GND - 1.0 V (t
UNDER
< 50 ns)
Overshoot/Undershoot
t
UNDER
< 50 ns
V
IOVER
< V
DD
+ 1.0 V
V
DD
GND
V
IUNDER
< GND - 1.0 V
Input pin
t
OVER
< 50 ns
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
3.3
Max.
+85
3.6
Units
°C
V
MDS 7151A-50 A
Integrated Circuit Systems, Inc.
●
4
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
ICS7151A-50
Spread Spectrum Clock Generator
DC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±0.3 V,
Ambient Temperature -40 to +85°C
Parameter
Operating Voltage
Supply Current
Input Frequency
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Capacitance
Symbol
VDD
IDD
Conditions
No load, at 3.3 V,
output = 24 MHz
Min.
3.0
Typ.
3.3
10
Max.
3.6
14
33.4
VDD + 0.3
VDD * 0.20
0.4
16
15
10
7
Units
V
mA
MHz
V
V
V
V
pF
pF
pF
pF
kΩ
16.5
V
IH
V
IL
V
OH
V
OL
C
IN
XIN, S0, S1, ENS
XIN, S0, S1, ENS
CKOUT, I
OH
= -4 mA
CKOUT, I
OL
= 4 mA
XIN, S0, S1, ENS
CKOUT, 8.3 to 66.7
MHz
VDD * 0.8
0.0
2.0
Load Capacitance
C
L
CKOUT, 66.7 to 100
MHz
CKOUT, 100 to 133.4
MHz
Input Pull-up Resistor
R
PU
ENS
100
240
400
AC Electrical Characteristics
Unless stated otherwise,
VDD = 3.3 V ±0.3 V,
Ambient Temperature -40 to +85° C
Parameter
Oscillation Frequency
Input Frequency
Output Frequency
Input Clock Duty Cycle
Output Clock Duty Cycle
Output Slew Rate
Cycle to Cycle Jitter
Lock Time
Modulation Frequency
Symbol
f
X
f
IN
f
OUT
Conditions
Fundamental
oscillation
XIN
CKOUT, 2-frequency
division
XIN, 16.5 to 33.4 MHz
CKOUT, 1.5 V
CKOUT, 0.4 to 2.4 V,
load capacitance 15 pF
Min.
16.5
16.5
8.3
40
40
0.5
Typ.
Max.
33.4
33.4
16.7
Units
MHz
MHz
MHz
%
%
V/ns
ps
ms
kHz
50
TBD
TBD
2
33
60
60
3.0
200
5
t
DCC
t
JC
t
LK
f
MOD
No load, standard
deviation
CKOUT
CKOUT=TBD
MDS 7151A-50 A
Integrated Circuit Systems, Inc.
●
5
525 Race Street, San Jose, CA 95126
●
Revision 102005
tel (408) 297-1201
●
www.icst.com
