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IDT54FCT273CTD

D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDIP20, CERDIP-20

器件类别：逻辑    逻辑   

厂商名称：IDT (Integrated Device Technology)

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参数 预览 参数对比
器件参数
参数名称
属性值
零件包装代码
DIP
包装说明
DIP,
针数
20
Reach Compliance Code
unknown
系列
FCT
JESD-30 代码
R-GDIP-T20
JESD-609代码
e0
长度
25.3365 mm
逻辑集成电路类型
D FLIP-FLOP
位数
8
功能数量
1
端子数量
20
最高工作温度
125 °C
最低工作温度
-55 °C
输出极性
TRUE
封装主体材料
CERAMIC, GLASS-SEALED
封装代码
DIP
封装形状
RECTANGULAR
封装形式
IN-LINE
传播延迟（tpd）
6.5 ns
认证状态
Not Qualified
座面最大高度
5.08 mm
最大供电电压 (Vsup)
5.5 V
最小供电电压 (Vsup)
4.5 V
标称供电电压 (Vsup)
5 V
表面贴装
NO
技术
CMOS
温度等级
MILITARY
端子面层
TIN LEAD
端子形式
THROUGH-HOLE
端子节距
2.54 mm
端子位置
DUAL
触发器类型
POSITIVE EDGE
宽度
7.62 mm
Base Number Matches
1
文档预览
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
FAST CMOS
OCTAL D FLIP-FLOP
WITH MASTER RESET
FEATURES:
−
−
−
−
−
−
−
−
−
Std., A, and C speed grades
Low input and output leakage
≤1µ
A (max.)
CMOS power levels
True TTL input and output compatibility
•
V
OH
= 3.3V (typ.)
•
V
OL
= 0.3V (typ.)
High drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Military product compliant to MIL-STD-883, Class B and DESC
listed (dual marked)
Power off disable outputs permit “live insertion”
Available in the following packages:
•
Industrial: SOIC, SSOP, QSOP
•
Military: CERDIP, LCC, CERPACK
IDT54/74FCT273T/AT/CT
DESCRIPTION:
The FCT273T is an octal D flip-flop built using an advanced dual metal
CMOS technology. The FCT273T has eight edge-triggered D-type flip-
flops with individual D inputs and O outputs. The common buffered Clock
(CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops
simultaneously.
The register is fully edge-triggered. The state of each D input, one set-
up time before the low-to-high clock transition, is transferred to the corre-
sponding flip-flop’s O output.
All outputs will be forced low independently of Clock or Data inputs by
a low voltage level on the
MR
input. The device is useful for applications
where the true output only is required and the Clock and Master Reset are
common to all storage elements.
FUNCTIONAL BLOCK DIAGRAM
D
0
CP
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
CP
R
D
MR
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
D
CP
R
D
Q
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
c
2001 Integrated Device Technology, Inc.
MAY 2001
DSC-2568/-
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
O
0
MR
O
0
D
0
D
1
O
1
O
2
D
2
D
3
O
3
GND
1
2
3
4
5
6
7
8
9
10
D20-1
SO20-2
SO20-7
SO20-8
E20-1
20
19
18
17
16
15
14
13
12
11
V
CC
O
7
D
0
3
2
1
D
7
D
6
O
6
O
5
D
5
D
4
O
4
CP
20
19
18
17
D
1
O
1
O
2
D
2
D
3
O
7
INDEX
MR
V
CC
4
5
6
7
8
9
10
D
7
D
6
O
6
O
5
D
5
L20-2
16
15
14
11
12
13
O
3
CERDIP/ SOIC/ SSOP/ QSOP/ CERPACK
TOP VIEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM(2)
V
TERM(3)
T
STG
I
OUT
Rating
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max.
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
8T-link
PIN DESCRIPTION
Pin Names
D
N
MR
CP
O
N
Description
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or
any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
No
terminal voltage may exceed Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Outputs and I/O terminals only.
FUNCTION TABLE
(1)
Operating Mode
Reset (Clear)
Load "1"
Load "0"
MR
L
H
H
Inputs
CP
X
↑
↑
D
N
X
h
I
Outputs
O
N
L
H
L
CAPACITANCE
(T
A
= +25
O
C, f = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
8T-link
NOTE:
1. This parameter is measured at characterization but not tested.
NOTE:
1. H = HIGH voltage level steady state
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock
transition
L = LOW voltage level steady state
I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock
transition
X = Don’t Care
↑
= LOW-to-HIGH Clock Transition
2
GND
LCC
TOP VIEW
CP
O
4
D
4
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Commercial: T
A
= –40°C to +85°C, V
CC
= 5.0V ± 5%; Military: T
A
= –55°C to +125°C, V
CC
= 5.0V ± 10%
Symbol
V
IH
V
IL
I
IH
I
IL
I
I
V
IK
I
OS
V
OH
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
Input HIGH Current
(4)
Clamp Diode Voltage
Short Circuit Current
Output HIGH Voltage
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
N
= –18mA
V
CC
= Max.
(3)
, V
O
= GND
V
CC
= Min.
V
IN
= V
IH
or V
IL
I
OH
= –6mA MIL
I
OH
= –8mA IND
I
OH
= –12mA MIL
I
OH
= –15mA IND
I
OL
= 32mA MIL
I
OL
= 48mA IND
—
Min.
2
—
—
—
—
—
–60
2.4
2
—
—
—
Typ.
(2)
—
—
—
—
—
–0.7
–120
3.3
3
0.3
200
0.01
Max.
—
0.8
±1
±1
±1
–1.2
–225
—
—
0.5
—
1
Unit
V
V
µA
µA
µA
V
mA
V
V
I
= 2.7V
V
I
= 0.5V
V
OL
V
H
I
CC
Output LOW Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Min.
V
IN
= V
IH
or V
IL
V
CC
= Max.
V
IN
=
GND or
V
CC
V
mV
mA
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be shorted at one time. Duration of the short circuit test should not exceed one second.
4. The test parameter for this parameter is ±5µA at T
A
= -55°C.
3
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current TTL
Inputs HIGH
Dynamic Power Supply Current
(4)
Test Conditions
(1)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
MR
= V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
=
V
CC
One Bit Toggling
at f
i
= 5MHz
50% Duty Cycle
V
CC
= Max.
Outputs Open
f
CP
= 10MHz
50% Duty Cycle
MR
=
V
CC
Eight Bits Toggling
at f
i
= 2.5MHz
50% Duty Cycle
Min.
—
V
IN
= V
CC
V
IN
= GND
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
—
1.5
3.5
mA
V
IN
= 3.4V
V
IN
= GND
—
2
5.5
V
IN
= V
CC
V
IN
= GND
—
3.8
7.3
(5)
V
IN
= 3.4V
V
IN
= GND
—
6
16.3
(
5)
NOTES:
1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V); all other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(f
CP
/2 + f
i
N
i
)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current Caused by an Input Transition Pair (HLH or LHL)
f
CP
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
f
i
= Input Frequency
N
i
= Number of Inputs at f
i
All currents are in milliamps and all frequencies are in megahertz.
4
IDT54/74FCT273T/AT/CT
FAST CMOS OCTAL D FLIP-FLOP WITH MASTER RESET
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - INDUSTRIAL
IDT74FCT273T
Symbol
t
PLH
t
PHL
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
CP to O
N
Propagation Delay
MR
to O
N
Set-up Time HIGH or LOW D
N
to CP
Hold Time HIGH or LOW D
N
to CP
CP Pulse Width HIGH or LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min
. (2)
2
2
3
2
7
7
4
Max
.
13
13
—
—
—
—
—
IDT74FCT273AT
Min
. (2)
2
2
2
1.5
6
6
2
Max
.
7.2
7.2
—
—
—
—
—
IDT74FCT273CT
Min
. (2)
2
2
2
1.5
6
6
2
Max
.
5.8
6.1
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY
IDT74FCT273T
Symbol
t
PLH
t
PHL
t
PHL
t
SU
t
H
t
W
t
W
t
REM
Parameter
Propagation Delay
CP to O
N
Propagation Delay
MR
to O
N
Set-up Time HIGH or LOW D
N
to CP
Hold Time HIGH or LOW D
N
to CP
CP Pulse Width HIGH or LOW
MR
Pulse Width LOW
Recovery Time
MR
to CP
Condition
(1)
C
L
= 50pF
R
L
= 500Ω
Min
. (2)
2
2
3.5
2
7
7
5
Max
.
15
15
—
—
—
—
—
IDT74FCT273AT
Min
. (2)
2
2
2
1.5
6
6
2.5
Max
.
8.3
8.3
—
—
—
—
—
IDT74FCT273CT
Min
. (2)
2
2
2
1.5
6
6
2.5
Max
.
6.5
6.8
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
5
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参数对比
与IDT54FCT273CTD相近的元器件有：5962-9221505M2A、5962-9221501M2A、5962-9221501MRA、IDT54FCT273CTDB、IDT54FCT273CTLB、5962-9221505MRA、IDT54FCT273ATDB、5962-9221503M2A、IDT54FCT273CTEB。描述及对比如下：
型号 IDT54FCT273CTD 5962-9221505M2A 5962-9221501M2A 5962-9221501MRA IDT54FCT273CTDB IDT54FCT273CTLB 5962-9221505MRA IDT54FCT273ATDB 5962-9221503M2A IDT54FCT273CTEB
描述 D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDIP20, CERDIP-20 LCC-20, Tube LCC-20, Tube CDIP-20, Tube D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDIP20, CERAMIC, DIP-20 D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CQCC20, LCC-20 CDIP-20, Tube D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDIP20, CERAMIC, DIP-20 LCC-20, Tube D Flip-Flop, FCT Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, CMOS, CDFP20, CERPACK-20
零件包装代码 DIP LCC LCC CDIP DIP QLCC CDIP DIP LCC DFP
包装说明 DIP, QCCN, LCC20,.35SQ QCCN, LCC20,.35SQ DIP, DIP20,.3 CERAMIC, DIP-20 QCCN, LCC20,.35SQ DIP, DIP20,.3 CERAMIC, DIP-20 LCC-20 DFP, FL20,.3
针数 20 20 20 20 20 20 20 20 20 20
Reach Compliance Code unknown not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant not_compliant _compli
系列 FCT FCT FCT FCT FCT FCT FCT FCT FCT FCT
JESD-30 代码 R-GDIP-T20 S-CQCC-N20 S-CQCC-N20 R-GDIP-T20 R-GDIP-T20 S-CQCC-N20 R-GDIP-T20 R-GDIP-T20 S-CQCC-N20 R-GDFP-F20
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0 e0 e0
逻辑集成电路类型 D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP
位数 8 8 8 8 8 8 8 8 8 8
功能数量 1 1 1 1 1 1 1 1 1 1
端子数量 20 20 20 20 20 20 20 20 20 20
最高工作温度 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C 125 °C
最低工作温度 -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C -55 °C
输出极性 TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE TRUE
封装主体材料 CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED CERAMIC, GLASS-SEALED CERAMIC, METAL-SEALED COFIRED CERAMIC, GLASS-SEALED
封装代码 DIP QCCN QCCN DIP DIP QCCN DIP DIP QCCN DFP
封装形状 RECTANGULAR SQUARE SQUARE RECTANGULAR RECTANGULAR SQUARE RECTANGULAR RECTANGULAR SQUARE RECTANGULAR
封装形式 IN-LINE CHIP CARRIER CHIP CARRIER IN-LINE IN-LINE CHIP CARRIER IN-LINE IN-LINE CHIP CARRIER FLATPACK
传播延迟（tpd） 6.5 ns 6.5 ns 15 ns 15 ns 6.5 ns 6.5 ns 6.5 ns 8.3 ns 8.3 ns 6.5 ns
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
座面最大高度 5.08 mm 2.54 mm 2.54 mm 5.08 mm 5.08 mm 2.54 mm 5.08 mm 5.08 mm 2.54 mm 2.337 mm
最大供电电压 (Vsup) 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V 5.5 V
最小供电电压 (Vsup) 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V 4.5 V
标称供电电压 (Vsup) 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
表面贴装 NO YES YES NO NO YES NO NO YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY MILITARY
端子面层 TIN LEAD Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn63Pb37) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 THROUGH-HOLE NO LEAD NO LEAD THROUGH-HOLE THROUGH-HOLE NO LEAD THROUGH-HOLE THROUGH-HOLE NO LEAD FLAT
端子节距 2.54 mm 1.27 mm 1.27 mm 2.54 mm 2.54 mm 1.27 mm 2.54 mm 2.54 mm 1.27 mm 1.27 mm
端子位置 DUAL QUAD QUAD DUAL DUAL QUAD DUAL DUAL QUAD DUAL
触发器类型 POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
宽度 7.62 mm 8.89 mm 8.89 mm 7.62 mm 7.62 mm 8.89 mm 7.62 mm 7.62 mm 8.89 mm 6.9215 mm
长度 25.3365 mm 8.89 mm 8.89 mm 25.3365 mm 25.3365 mm 8.89 mm 25.3365 mm 25.3365 mm 8.89 mm -
Base Number Matches 1 1 1 1 1 1 1 1 1 -
是否Rohs认证 - 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
负载电容（CL） - 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF 50 pF
最大频率@ Nom-Sup - 83300000 Hz 71400000 Hz 71400000 Hz 83300000 Hz 83300000 Hz 83300000 Hz 83300000 Hz 83300000 Hz -
最大I（ol） - 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A 0.032 A
封装等效代码 - LCC20,.35SQ LCC20,.35SQ DIP20,.3 DIP20,.3 LCC20,.35SQ DIP20,.3 DIP20,.3 LCC20,.35SQ FL20,.3
峰值回流温度（摄氏度） - 240 240 240 225 225 240 225 240 -
电源 - 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V 5 V
Prop。Delay @ Nom-Sup - 6.5 ns 15 ns 15 ns 6.5 ns 6.5 ns 6.5 ns 8.3 ns 8.3 ns -
筛选级别 - MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 Class B MIL-STD-883 Class B MIL-STD-883 MIL-STD-883 Class B MIL-STD-883 MIL-STD-883 Class B
处于峰值回流温度下的最长时间 - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED 20 30 NOT SPECIFIED 20 NOT SPECIFIED -
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