IDT70V3589S133DRG,IDT70V3589S133DRG pdf中文资料,IDT70V3589S133DRG引脚图,IDT70V3589S133DRG电路-Datasheet-电子工程世界

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HIGH-SPEED 3.3V

128/64K x 36

SYNCHRONOUS

IDT70V3599/89S

DUAL-PORT STATIC RAM

WITH 3.3V OR 2.5V INTERFACE

Features:

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed data access

– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

– Industrial: 4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without

additional logic

Full synchronous operation on both ports

– 6ns cycle time, 166MHz operation (12Gbps bandwidth)

– Fast 3.6ns clock to data out

– 1.7ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 166MHz

– Data input, address, byte enable and control registers

– Self-timed write allows fast cycle time

◆

Separate byte controls for multiplexed bus and bus

matching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output mode

LVTTL- compatible, 3.3V (±150mV) power supply

for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V

(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) is

available at 133MHz.

Available in a 208-pin Plastic Quad Flatpack (PQFP),

208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball

Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1

Green parts available, see ordering information

Functional Block Diagram

FT/PIPE

1/0

0a 1a

0b 1b

0c 1c

0d 1d

1d 0d

1c 0c

1b 0b

1a 0a

1/0

FT/PIPE

R/W

1/0

B B B

WWW

2 3 3

L L R

B B

1 0

R R

1 /0

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

1d 0d

1c 0c 1b 0b 1a 0a

a b cd

0a 1a 0b 1b

0c 1c 0d 1d

0/1

FT/PIPE

0/1

FT/PIPE

d cba

128K x 36

MEMORY

ARRAY

I/O

- I/O

35 L

Din_L

Din_R

I/O

- I/O

35R

CLK

16L (1)

REPEAT

ADS

CNTEN

CLK

16R

(1)

Counter/

Address

Reg.

ADDR_L

ADDR_R

Counter/

Address

Reg.

REPEAT

ADS

CNTEN

5617 tbl 01

TDI

NOTE:

1. A

is a NC for IDT70V3589.

JTAG

TDO

TCK

TMS

TRST

JULY 2010

DSC 5617/9

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Description:

The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to

allow simultaneous access of any address from both ports. Registers on

control, data, and address inputs provide minimal setup and hold

times. The timing latitude provided by this approach allows systems

to be designed with very short cycle times. With an input data register, the

IDT70V3599/89 has been optimized for applications having unidirectional

or bidirectional data flow in bursts. An automatic power down feature,

controlled by

and CE

permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70V3599/89 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power supply

for the core of the device (V

) remains at 3.3V.

Pin Configuration

(1,2,3,4,5)

06/28/02

A10

A11

A12

A13

A14

A15

A16

A17

19L

18L

TDO

16L

(1)

12L

B10

CLK

CNTEN

B11

B12

B13

B14

OPT

I/O

17L

B15

B16

B17

I/O

20R

I/O

18R

TDI

13L

C10

ADS

C11

C12

C13

C14

DDQR

I/O

16L

I/O

15R

C15

C16

C17

DDQL

I/O

19R

DDQR

PL/

14L

10L

D10

R/W

D11

D12

D13

D14

I/O

16R

I/O

15L

D15

D16

D17

I/O

22L

I/O

21L

I/O

20L

15L

11L

REPEAT

I/O

17R

DDQL

I/O

14L

I/O

14R

E14

E15

E16

E17

I/O

23L

I/O

22R

DDQR

I/O

21R

I/O

12L

I/O

13R

F14

F15

F16

I/O

13L

F17

DDQL

I/O

23R

I/O

24L

G14

I/O

12R

I/O

11L

DDQR

G15

G16

G17

I/O

26L

I/O

25L

I/O

24R

I/O

DDQL

I/O

10L

I/O

11R

I/O

26R

DDQR

I/O

25R

70V3599/89BF

BF-208

(6)

208-Pin fpBGA

Top View

(7)

H14

H15

H16

H17

J14

J15

J16

I/O

10R

J17

DDQL

K14

K15

DDQR

K16

K17

I/O

28R

I/O

27R

I/O

DDQL

I/O

L14

L15

L16

L17

I/O

29R

I/O

28L

DDQR

I/O

27L

I/O

M14

I/O

M15

M16

I/O

M17

DDQL

I/O

29L

I/O

30R

N14

I/O

DDQR

N15

N16

N17

I/O

31L

I/O

31R

I/O

30L

P10

P11

P12

P13

I/O

DDQL

I/O

P14

P15

P16

I/O

P17

I/O

32R

I/O

32L

DDQR

I/O

35R

TRST

16R

(1)

12R

R10

CLK

CNTEN

R11

R12

R13

I/O

R14

R15

R16

I/O

R17

I/O

33L

I/O

34R

TCK

13R

T10

ADS

T11

T12

T13

T14

DDQL

T15

I/O

DDQR

T16

T17

I/O

33R

I/O

34L

DDQL

TMS

14R

10R

U10

R/W

U12

U13

U14

I/O

U15

U16

I/O

U17

I/O

35L

PL/

15R

11R

OPT

I/O

NOTES:

5617 drw 02c

1. A

is a NC for IDT70V3589.

2. All V

pins must be connected to 3.3V power supply.

3. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

4. All V

pins must be connected to ground supply.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,5)

(con't.)

70V3599/89BC

BC-256

(6)

06/28/02

256-Pin BGA

Top View

(7)

A10

A11

A12

A13

A14

A15

A16

TDI

14L

11L

CNTEN

B10

B11

B12

B13

B14

B15

B16

I/O

18L

TDO

15L

12L

R/W

REPEAT

C10

C11

C12

C13

C14

I/O

17L

C15

C16

I/O

18R

I/O

19L

16L

(1)

13L

10L

CLK

ADS

D10

D11

D12

D13

OPT

I/O

17R

I/O

16L

D14

D15

D16

I/O

20R

I/O

19R

I/O

20L

PIPE/

DDQL

DDQR

DDQL

DDQR

I/O

15R

I/O

15L

I/O

16R

E10

E11

E12

E13

E14

E15

E16

I/O

21R

I/O

21L

I/O

22L

DDQL

F10

F11

DDQR

I/O

13L

I/O

14L

I/O

14R

F12

F13

F14

F15

F16

I/O

23L

I/O

22R

I/O

23R

DDQL

G10

G11

G12

DDQR

I/O

12R

I/O

13R

I/O

12L

G13

G14

G15

G16

I/O

24R

I/O

24L

I/O

25L

DDQR

H10

H11

H12

DDQL

I/O

10L

I/O

11L

I/O

11R

H13

H14

H15

H16

I/O

26L

I/O

25R

I/O

26R

DDQR

J10

J11

J12

DDQL

I/O

J13

J14

I/O

10R

J15

J16

I/O

27L

I/O

28R

I/O

27R

DDQL

K10

K11

K12

DDQR

I/O

K13

K14

K15

I/O

K16

I/O

29R

I/O

29L

I/O

28L

DDQL

L10

L11

L12

DDQR

I/O

L13

L14

I/O

L15

I/O

L16

I/O

30L

I/O

31R

I/O

30R

DDQR

M10

M11

M12

DDQL

I/O

M13

M14

I/O

M15

M16

I/O

32R

I/O

32L

I/O

31L

DDQR

N10

N11

N12

DDQL

I/O

N13

N14

I/O

N15

I/O

N16

I/O

33L

I/O

34R

I/O

33R

PIPE/

DDQR

DDQL

DDQR

DDQL

P10

P11

P12

P13

I/O

P14

I/O

P15

P16

I/O

35R

I/O

34L

TMS A

16R

(1)

13R

10R

CLK

ADS

R10

R11

R12

R13

I/O

R14

R15

I/O

R16

I/O

35L

TRST

15R

12R

R/W

REPEAT

T10

T11

T12

T13

OPT

T14

T15

T16

TCK

14R

11R

CNTEN

5617 drw 02d

NOTES:

1. A

is a NC for IDT70V3589.

2. All V

pins must be connected to 3.3V power supply.

3. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

4. All V

pins must be connected to ground supply.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

6. This package code is used to reference the package diagram.

7. This text does not indicate orientation of the actual part-marking.

6.42

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,5)

(con't.)

06/28/02

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

DDQR

I/O

18R

I/O

18L

PL/FT

TDI

TDO

16L

(1)

15L

14L

13L

12L

11L

10L

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

17L

I/O

17R

DDQR

100

101

102

103

104

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

70V3599/89DR

DR-208

(6)

208-Pin PQFP

Top View

(7)

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

NOTES:

A16 is a NC for IDT70V3589.

All V

pins must be connected to 3.3V power supply.

All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

All V

pins must be connected to ground supply.

Package body is approximately 28mm x 28mm x 3.5mm.

This package code is used to reference the package diagram.

This text does not indicate orientation of the actual part-marking.

DDQL

I/O

35R

I/O

35L

PL/FT

TMS

TCK

TRST

16R

(1)

15R

14R

13R

12R

11R

10R

CLK

R/W

ADS

CNTEN

REPEAT

OPT

I/O

DDQL

5617 drw 02a

6.42

IDT70V3599/89S

High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM

Industrial and Commercial Temperature Ranges

Pin Names

Left Port

R/W

- A

16L

(1)

I/O

- I/O

35L

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQL

OPT

TDI

TDO

TCK

TMS

TRST

Right Port

R/W

- A

16R

(1)

I/O

- I/O

35R

CLK

PL/FT

ADS

CNTEN

REPEAT

DDQR

OPT

Names

Chip Enables

(5)

Read/Write Enable

Output Enable

Address

Data Input/Output

Clock

Pipeline/Flow-Through

Address Strobe Enable

Counter Enable

Counter Repeat

(4)

Byte Enables (9-bit bytes)

(5)

Power (I/O Bus) (3.3V or 2.5V)

(2)

Option for selecting V

DDQX

(2,3)

Power (3.3V)

(2)

Ground (0V)

Test Data Input

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

5617 tbl 01

NOTES:

1. A

is a NC for IDT70V3589.

2. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

3. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another—both ports can

operate at 3.3V levels, both can operate at 2.5V levels, or either can operate

at 3.3V with the other at 2.5V.

4. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

5. Chip Enables and Byte Enables are double buffered when PL/FT = V

, i.e., the

signals take two cycles to deselect.

6.42

参数对比

与IDT70V3589S133DRG相近的元器件有：IDT70V3589S133DRGI、IDT70V3589S133DRGI8、IDT70V3599S133BFGI、IDT70V3599S133BFGI8、IDT70V3599S133BCGI、IDT70V3599S166DRG、IDT70V3599S166BFG8、IDT70V3589S133DRG8、IDT70V3599S133DRGI。描述及对比如下：

型号	IDT70V3589S133DRG	IDT70V3589S133DRGI	IDT70V3589S133DRGI8	IDT70V3599S133BFGI	IDT70V3599S133BFGI8	IDT70V3599S133BCGI	IDT70V3599S166DRG	IDT70V3599S166BFG8	IDT70V3589S133DRG8	IDT70V3599S133DRGI
描述	Dual-Port SRAM, 64KX36, 15ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, QFP-208	Dual-Port SRAM, 64KX36, 15ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, QFP-208	Application Specific SRAM, 64KX36, 4.2ns, CMOS, PQFP208	Dual-Port SRAM, 128KX36, 15ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, GREEN, FBGA-208	Dual-Port SRAM, 128KX36, 15ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FBGA-208	Dual-Port SRAM, 128KX36, 15ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, GREEN, BGA-256	Dual-Port SRAM, 128KX36, 12ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, QFP-208	Dual-Port SRAM, 128KX36, 12ns, CMOS, PBGA208, 15 X 15 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, FBGA-208	Application Specific SRAM, 64KX36, 4.2ns, CMOS, PQFP208	Dual-Port SRAM, 128KX36, 15ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM HEIGHT, GREEN, PLASTIC, QFP-208
是否无铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅	不含铅
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合	符合	符合
厂商名称	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)	IDT (Integrated Device Technology)
Reach Compliance Code	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant	compliant
ECCN代码	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A	3A991.B.2.A
最长访问时间	15 ns	15 ns	4.2 ns	15 ns	15 ns	15 ns	12 ns	12 ns	4.2 ns	15 ns
最大时钟频率 (fCLK)	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	133 MHz	166 MHz	166 MHz	133 MHz	133 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	S-PQFP-G208	S-PQFP-G208	S-PQFP-G208	S-PBGA-B208	S-PBGA-B208	S-PBGA-B256	S-PQFP-G208	S-PBGA-B208	S-PQFP-G208	S-PQFP-G208
JESD-609代码	e3	e3	e3	e1	e1	e1	e3	e1	e3	e3
内存密度	2359296 bit	2359296 bit	2359296 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	4718592 bit	2359296 bit	4718592 bit
内存集成电路类型	DUAL-PORT SRAM	DUAL-PORT SRAM	APPLICATION SPECIFIC SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	DUAL-PORT SRAM	APPLICATION SPECIFIC SRAM	DUAL-PORT SRAM
内存宽度	36	36	36	36	36	36	36	36	36	36
湿度敏感等级	3	3	3	3	3	3	3	3	3	3
端口数量	2	2	2	2	2	2	2	2	2	2
端子数量	208	208	208	208	208	256	208	208	208	208
字数	65536 words	65536 words	65536 words	131072 words	131072 words	131072 words	131072 words	131072 words	65536 words	131072 words
字数代码	64000	64000	64000	128000	128000	128000	128000	128000	64000	128000
工作模式	SYNCHRONOUS	SYNCHRONOUS	ASYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	ASYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	85 °C	85 °C	85 °C	85 °C	85 °C	70 °C	70 °C	70 °C	85 °C
最低工作温度	-	-40 °C	-40 °C	-40 °C	-40 °C	-40 °C	-	-	-	-40 °C
组织	64KX36	64KX36	64KX36	128KX36	128KX36	128KX36	128KX36	128KX36	64KX36	128KX36
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	FQFP	FQFP	QFP	LFBGA	LFBGA	LBGA	FQFP	LFBGA	QFP	FQFP
封装等效代码	QFP208,1.2SQ,20	QFP208,1.2SQ,20	QFP208,1.2SQ,20	BGA208,17X17,32	BGA208,17X17,32	BGA256,16X16,40	QFP208,1.2SQ,20	BGA208,17X17,32	QFP208,1.2SQ,20	QFP208,1.2SQ,20
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	FLATPACK, FINE PITCH	FLATPACK, FINE PITCH	FLATPACK	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE	FLATPACK, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	FLATPACK	FLATPACK, FINE PITCH
并行/串行	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL	PARALLEL
峰值回流温度（摄氏度）	260	260	260	260	260	260	260	260	260	260
电源	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V	2.5/3.3,3.3 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
最大待机电流	0.03 A	0.04 A	0.04 A	0.04 A	0.04 A	0.04 A	0.03 A	0.03 A	0.03 A	0.04 A
最小待机电流	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V
最大压摆率	0.4 mA	0.48 mA	0.48 mA	0.48 mA	0.48 mA	0.48 mA	0.5 mA	0.5 mA	0.4 mA	0.48 mA
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	INDUSTRIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL
端子面层	Matte Tin (Sn)	Matte Tin (Sn)	Matte Tin (Sn)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn)	Tin/Silver/Copper (Sn/Ag/Cu)	Matte Tin (Sn)	Matte Tin (Sn)
端子形式	GULL WING	GULL WING	GULL WING	BALL	BALL	BALL	GULL WING	BALL	GULL WING	GULL WING
端子节距	0.5 mm	0.5 mm	0.5 mm	0.8 mm	0.8 mm	1 mm	0.5 mm	0.8 mm	0.5 mm	0.5 mm
端子位置	QUAD	QUAD	QUAD	BOTTOM	BOTTOM	BOTTOM	QUAD	BOTTOM	QUAD	QUAD
处于峰值回流温度下的最长时间	30	30	30	30	30	30	30	30	30	30
零件包装代码	QFP	QFP	-	BGA	BGA	BGA	QFP	BGA	-	QFP
包装说明	FQFP, QFP208,1.2SQ,20	FQFP, QFP208,1.2SQ,20	QFP, QFP208,1.2SQ,20	LFBGA, BGA208,17X17,32	LFBGA, BGA208,17X17,32	LBGA, BGA256,16X16,40	FQFP, QFP208,1.2SQ,20	LFBGA, BGA208,17X17,32	-	FQFP, QFP208,1.2SQ,20
针数	208	208	-	208	208	256	208	208	-	208
其他特性	PIPELINED OR FLOW-THROUGH ARCHITECTURE	PIPELINED OR FLOW-THROUGH ARCHITECTURE	-	PIPELINED OR FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	PIPELINED OR FLOW-THROUGH ARCHITECTURE	PIPELINED OR FLOW-THROUGH ARCHITECTURE	FLOW-THROUGH OR PIPELINED ARCHITECTURE	-	PIPELINED OR FLOW-THROUGH ARCHITECTURE
长度	28 mm	28 mm	-	15 mm	15 mm	17 mm	28 mm	15 mm	-	28 mm
功能数量	1	1	-	1	1	1	1	1	-	1
座面最大高度	4.1 mm	4.1 mm	-	1.7 mm	1.7 mm	1.7 mm	4.1 mm	1.7 mm	-	4.1 mm
最大供电电压 (Vsup)	3.45 V	3.45 V	-	3.45 V	3.45 V	3.45 V	3.45 V	3.45 V	-	3.45 V
最小供电电压 (Vsup)	3.15 V	3.15 V	-	3.15 V	3.15 V	3.15 V	3.15 V	3.15 V	-	3.15 V
标称供电电压 (Vsup)	3.3 V	3.3 V	-	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	-	3.3 V
宽度	28 mm	28 mm	-	15 mm	15 mm	17 mm	28 mm	15 mm	-	28 mm