IS61vPS102436A IS61lPS102436A
IS61vPS204818A IS61lPS204818A
1Mb x 36, 2Mb x 18
36Mb SYNCHRONOUS PIPElINED,
SINglE CYClE DESElECT STATIC RAM
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Burst sequence control using MODE input
• Three chip enable option for simple depth ex-
pansion and address pipelining
• Common data inputs and data outputs
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• Power Supply
LPS: V
dd
3.3V + 5%,
V
ddq
3.3V/2.5V + 5%
VPS: V
dd
2.5V + 5%,
V
ddq
2.5V + 5%
• JEDEC 100-Pin TQFP and 165-ball PBGA
packages
• Lead-free available
JUNE 2010
DESCRIPTION
The
ISSI
IS61LPS/VPS102436A and IS61LPS/VPS
204818A are high-speed, low-power synchronous static
RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61LPS/VPS102436A is organized as 1,048,476
words by 36 bits. The IS61LPS/VPS204818A is organized
as 2M-word by 18 bits. Fabricated with
ISSI
's advanced
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-
edge-triggered single clock input.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be
one to four bytes wide as controlled by the write control
inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (BWE) input combined with one or more
individual byte write signals (BWx). In addition, Global
Write (GW) is available for writing all bytes at one time,
regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or
ADSC
(Address Status Cache Controller)
input pins. Subsequent burst addresses can be gener-
ated internally and controlled by the
ADV
(burst address
advance) input pin.
The mode pin is used to select the burst sequence or-
der, Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH
or left floating.
FAST ACCESS TIME
Symbol
t
kq
t
kc
Parameter
Clock Access Time
Cycle Time
Frequency
200
3.1
5
200
166
3.5
6
166
Units
ns
ns
MHz
Copyright © 2010 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written
assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
1
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
BLOCK DIAGRAM
MODE
CLK
CLK
Q0
A0
A0'
BINARY
COUNTER
ADV
ADSC
ADSP
CE
CLR
Q1
A1
A1'
1Mx36;
2Mx18
MEMORY ARRAY
20/21
A
20/21
D
Q
18/19
ADDRESS
REGISTER
CE
CLK
36,
or 18
36,
or 18
GW
BWE
BW(a-h)
x18: a,b
x36: a-d
DQ(a-h)
BYTE WRITE
REGISTERS
CLK
D
Q
CE
CE2
CE2
D
Q
2/4/8
ENABLE
REGISTER
CE
CLK
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
36,
or 18
DQa - DQd
OE
D
Q
ZZ
POWER
DOWN
ENABLE
DELAY
REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165-PIN BgA
165-Ball, 13x15 mm BGA
1mm Ball Pitch, 11x15 Ball Array
BOTTOM VIEW
Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
3
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
1M
x
36 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
l
M
N
P
R
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
2
A
A
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
A
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWc
BWd
Vss
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
Vss
A
A
5
BWb
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
A
1
*
A
0
*
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
8
ADSC
OE
Vss
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
Vss
A
A
9
ADV
ADSP
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
Nc
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
Nc
DQb
DQb
DQb
DQb
Nc
dqa
dqa
dqa
dqa
NC
A
A
11
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
dqa
dqa
dqa
dqa
DQPa
A
A
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2,
CE2
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
V
dd
V
ddq
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V
/2.5V
Ground
BWx (x=a,b,c,d)
Synchronous Byte Write
Controls
4
Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
IS61VPS102436A, IS61LPS102436A, IS61VPS204818A, IS61LPS204818A
165 PBGA PACKAGE PIN CONFIGURATION
2M
x
18 (TOP VIEW)
1
A
B
C
D
E
F
g
H
J
K
l
M
N
P
R
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
2
A
A
NC
DQb
DQb
DQb
DQb
NC
NC
NC
NC
NC
NC
NC
A
3
CE
CE2
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
NC
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
4
BWb
NC
Vss
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
Vss
A
A
5
NC
BWa
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
6
CE2
CLK
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
A
A
1
*
A
0
*
7
BWE
GW
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
NC
NC
NC
8
ADSC
OE
Vss
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
V
dd
Vss
A
A
9
ADV
ADSP
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
Nc
V
ddq
V
ddq
V
ddq
V
ddq
V
ddq
A
A
10
A
A
Nc
NC
NC
NC
NC
Nc
dqa
dqa
dqa
dqa
NC
A
A
11
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
Nc
Nc
Nc
Nc
NC
A
A
Note:
* A
0
and A
1
are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
A
A0, A1
ADV
ADSP
ADSC
GW
CLK
CE, CE2,
CE2
BWx (x=a,b)
Pin Name
Address Inputs
Synchronous Burst Address Inputs
Synchronous Burst Address
Advance
Address Status Processor
Address Status Controller
Global Write Enable
Synchronous Clock
Synchronous Chip Select
Synchronous Byte Write
Controls
Symbol
BWE
OE
ZZ
MODE
NC
DQx
DQPx
V
dd
V
ddq
Vss
Pin Name
Byte Write Enable
Output Enable
Power Sleep Mode
Burst Sequence Selection
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
3.3V/2.5V Power Supply
Isolated Output Power Supply
3.3V/2.5V
Ground
Integrated Silicon Solution, Inc.
Rev. C
05/27/2010
5
