IMPORTANT NOTICE
Dear customer,
As from August 2
nd
2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
●
Company name - NXP B.V.
is replaced with
ST-NXP Wireless.
Copyright
- the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site
-
http://www.nxp.com
is replaced with
http://www.stnwireless.com
Contact information
- the list of sales offices previously obtained by sending
an email to
salesaddresses@nxp.com
, is now found at
http://www.stnwireless.com
under Contacts.
●
●
●
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
www.stnwireless.com
ISP1512A
ULPI Hi-Speed USB transceiver
Rev. 01 — 31 July 2008
Preliminary data sheet
1. General description
The ISP1512A is a UTMI+ Low Pin Interface (ULPI) Hi-Speed Universal Serial Bus (USB)
transceiver that is fully compliant with
Universal Serial Bus Specification Rev. 2.0
and
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1.
The ISP1512A can transmit and receive USB data at high-speed (480 Mbit/s), full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s), and provides a pin-optimized, physical layer
front-end attachment to the USB host, peripheral and OTG controller with Single Data
Rate (SDR) ULPI link. The ISP1512A can transparently transmit and receive UART
signaling.
It is ideal for use in portable electronic devices, such as mobile phones, digital still
cameras, digital video cameras, Personal Digital Assistants (PDAs) and digital audio
players. It allows USB Application-Specific Integrated Circuits (ASICs), Programmable
Logic Devices (PLDs) or any system chip set to interface with the physical layer of the
USB through a 12-pin SDR interface.
The ISP1512A can interface to devices with digital I/O voltages in the range of 1.65 V to
1.95 V.
The ISP1512A is available in WLCSP25 package.
2. Features
I
Fully complies with:
N
USB:
Universal Serial Bus Specification Rev. 2.0
N
ULPI:
UTMI+ Low Pin Interface (ULPI) Specification Rev. 1.1
I
Interfaces to USB host or peripheral cores; optimized for portable devices or system
ASICs with built-in ULPI link
I
Complete Hi-Speed USB physical front-end solution that supports high-speed
(480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
N
Integrated 45
Ω ±
10 % high-speed termination resistors, 1.5 kΩ
±
5 % full-speed
device pull-up resistor, and 15 kΩ
±
5 % host termination resistors
N
Integrated parallel-to-serial and serial-to-parallel converters to transmit and receive
N
USB clock and data recovery to receive USB data up to
±500
ppm
N
USB data synchronization from 60 MHz input to 480 MHz output during transmit
N
Insertion of stuff bits during transmit and discarding of stuff bits during receive
N
Non-Return-to-Zero Inverted (NRZI) encoding and decoding
N
Supports bus reset, suspend, resume and high-speed detection handshake (chirp)
I
Partial USB OTG physical front-end support
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
I
I
I
I
I
I
N
Supports Session Request Protocol (SRP) that adheres to
On-The-Go Supplement
to the USB 2.0 Specification Rev. 1.3
N
Complete control over USB termination resistors
N
Data line and V
BUS
pulsing session request methods
N
Integrated V
BUS
voltage comparators
Flexible system integration and very low current consumption, optimized for portable
devices
N
3.0 V to 4.5 V power supply input range
N
Internal voltage regulator supplies 2.7 V or 3.3 V and 1.8 V
N
Supports interfacing I/O voltage of 1.65 V to 1.95 V; separate I/O voltage supply
pins minimize crosstalk
N
Powers down internal regulators in power-down mode when V
CC(I/O)
is not present
or when the chip is deasserted
N
Typical operating current of 10 mA to 48 mA, depending on the USB speed and
bus utilization
N
Typical suspend current of 50
µA
N
Typical power-down state current 0.5
µA,
max 10
µA
N
3-state ULPI interface by the CHIP_SEL pin, allowing bus reuse by other
applications
Highly optimized ULPI compliant
N
60 MHz, 12-pin interface between the core and the transceiver, including an 8-bit
SDR data bus
N
Supports 60 MHz output clock configuration
N
Integrated Phase-Locked Loop (PLL) supporting input clock frequency of 19.2 MHz
N
Fully programmable ULPI-compliant register set
N
3-pin or 6-pin full-speed or low-speed serial mode
N
Internal Power-On Reset (POR) circuit
UART interface:
N
Supports transparent UART signaling on the DP and DM pins for UART accessory
applications
N
2.7 V UART signaling on the DP and DM pins
N
Entering UART mode by register setting
N
Exiting UART mode by asserting STP or by toggling the CHIP_SEL pin
Full industrial grade operating temperature range from
−40 °C
to +85
°C
ESD compliance:
N
JESD22-A114-B
±2
kV contact Human Body Model (HBM)
N
JESD22-A115-A
±200
V Machine Model (MM)
N
JESD22-C101-A
±500
V Charge Device Model (CDM)
N
IEC 61000-4-2
±8
kV contact on the DP and DM pins
Available in small WLCSP25 Restriction of Hazardous Substances (RoHS) compliant,
halogen-free and lead-free package
3. Applications
I
Mobile phone
I
Digital still camera
ISP1512A_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 31 July 2008
2 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
I
I
I
I
I
I
I
I
I
MP3 player
PDA
Digital TV
Digital Video Disc (DVD) recorder
External storage device
Printer
Scanner
Set-Top Box (STB)
Video camera
4. Ordering information
Table 1.
Part
Type number
ISP1512AUK
CHIP_SEL
polarity
Frequency
Ordering information
Package
Name
Description
Bump
pitch
Version
active LOW 19.2 MHz
WLCSP25 wafer level chip-size package;
25 bumps; body 2.24
×
2.21
×
0.6 mm
0.4 mm ISP1512xUK
5. Marking
Table 2.
Marking codes
Marking code
[1]
1512A
Type number
ISP1512AUK
[1]
The package marking is the first line of text on the IC package and can be used for IC identification.
ISP1512A_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 31 July 2008
3 of 55
NXP Semiconductors
ISP1512A
ULPI HS USB transceiver
6. Block diagram
CLOCK
8
A3
A1, A5, B1,
B2, B3, B4,
B5, C5
D5
D4
C4
REGISTER
MAP
USB DATA
DESERIALIZER
TERMINATION
RESISTORS
C1
DM
ULPI
INTERFACE
CONTROLLER
USB DATA
SERIALIZER
HI-SPEED
USB ATX
D1
DP
ULPI
INTERFACE
DATA
[7:0]
DIR
STP
NXT
CHIP_SEL
A2
DATA[1:0]
UART
BUFFER
AUTO CLOCK
FREQUENCY
SELECTION
ISP1512A
OTG MODULE
V
BUS
COMPARATORS
E2
V
BUS
GLOBAL
CLOCKS
XTAL1
XTAL2
V
CC(I/O)
E3
E4
A4
PLL
SRP CHARGE
AND DISCHARGE
RESISTORS
OSCILLATOR
interface voltage
internal power
D3
POWER-ON
RESET
TEST
REG1V8
REG3V3
VCC
E5
D2
E1
VOLTAGE
REGULATOR
POR
BAND GAP
REFERENCE
VOLTAGE
C2
V
REF
C3
RREF
GND
004aaa989
Fig 1.
Block diagram
ISP1512A_1
© NXP B.V. 2008. All rights reserved.
Preliminary data sheet
Rev. 01 — 31 July 2008
4 of 55
