Freescale Semiconductor
Technical Data
Document Number: MPC8343EAEC
Rev. 11, 09/2011
MPC8343EA PowerQUICC II Pro
Integrated Host Processor Hardware
Specifications
The MPC8343EA PowerQUICC II Pro is a next generation
PowerQUICC II integrated host processor. The
MPC8343EA contains a processor core built on Power
Architecture® technology with system logic for networking,
storage, and general-purpose embedded applications. For
functional characteristics of the processor, refer to the
MPC8349EA PowerQUICC II Pro Integrated Host
Processor Family Reference Manual.
To locate published errata or updates for this document, refer
to the MPC8343EA product summary page on our website,
as listed on the back cover of this document, or contact your
local Freescale sales office.
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 6
Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 11
RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 13
DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 15
DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Ethernet: Three-Speed Ethernet, MII Management . 22
USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
I
2
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 49
Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
System Design Information . . . . . . . . . . . . . . . . . . . 73
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 76
Document Revision History . . . . . . . . . . . . . . . . . . . 78
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© 2006–2011 Freescale Semiconductor, Inc. All rights reserved.
Overview
NOTE
The information in this document is accurate for revision 3.x silicon and
later (in other words, for orderable part numbers ending in A or B). For
information on revision 1.1 silicon and earlier versions, see the
MPC8343E
PowerQUICC II Pro Integrated Host Processor Hardware Specifications.
See
Section 22.1, “Part Numbers Fully Addressed by This Document,”
for
silicon revision level determination.
1
Overview
This section provides a high-level overview of the device features.
Figure 1
shows the major functional
units within the MPC8343EA.
Security
DUART
Dual I
2
C
Timers
GPIO
e300 Core
Interrupt
Controller
32KB
D-Cache
32KB
I-Cache
DDR
SDRAM
Controller
Local Bus
High-Speed
USB 2.0
Dual
Role
10/100/1000
Ethernet
10/100/1000
Ethernet
PCI
SEQ
DMA
Figure 1. MPC8343EA Block Diagram
Major features of the device are as follows:
• Embedded PowerPC e300 processor core; operates at up to 400 MHz
— High-performance, superscalar processor core
— Floating-point, integer, load/store, system register, and branch processing units
— 32-Kbyte instruction cache, 32-Kbyte data cache
— Lockable portion of L1 cache
— Dynamic power management
— Software-compatible with the other Freescale processor families that implement Power
Architecture technology
• Double data rate, DDR1/DDR2 SDRAM memory controller
— Programmable timing supporting DDR1 and DDR2 SDRAM
— 32- bit data interface, up to 266 MHz data rate
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Overview
•
•
— Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
— DRAM chip configurations from 64 Mbits to 1 Gbit with ×8/×16 data ports
— Full error checking and correction (ECC) support
— Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
— Contiguous or discontiguous memory mapping
— Read-modify-write support
— Sleep-mode support for SDRAM self refresh
— Auto refresh
— On-the-fly power management using CKE
— Registered DIMM support
— 2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
— Dual controllers designed to comply with IEEE 802.3™, 802.3u™, 820.3x™, 802.3z™,
802.3ac™ standards
— Ethernet physical interfaces:
– 1000 Mbps IEEE Std. 802.3 RGMII, IEEE Std. 802.3z RTBI, full-duplex
– 10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
— Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
— MII management interface for control and status
— Programmable CRC generation and checking
PCI interface
— Designed to comply with
PCI Specification Revision 2.3
— Data bus width:
– 32-bit data PCI interface operating at up to 66 MHz
— PCI 3.3-V compatible
— PCI host bridge capabilities
— PCI agent mode on PCI interface
— PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses and support for delayed read transactions
— Posting of processor-to-PCI and PCI-to-memory writes
— On-chip arbitration supporting five masters on PCI
— Accesses to all PCI address spaces
— Parity supported
— Selectable hardware-enforced coherency
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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3
Overview
•
•
— Address translation units for address mapping between host and peripheral
— Dual address cycle for target
— Internal configuration registers accessible from PCI
Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP,
IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four
crypto-channels, a controller, and a set of crypto execution units (EUs):
— Public key execution unit (PKEU) :
– RSA and Diffie-Hellman algorithms
– Programmable field size up to 2048 bits
– Elliptic curve cryptography
– F2m and F(p) modes
– Programmable field size up to 511 bits
— Data encryption standard (DES) execution unit (DEU)
– DES and 3DES algorithms
– Two key (K1, K2) or three key (K1, K2, K3) for 3DES
– ECB and CBC modes for both DES and 3DES
— Advanced encryption standard unit (AESU)
– Implements the Rijndael symmetric-key cipher
– Key lengths of 128, 192, and 256 bits
– ECB, CBC, CCM, and counter (CTR) modes
— XOR parity generation accelerator for RAID applications
— ARC four execution unit (AFEU)
– Stream cipher compatible with the RC4 algorithm
– 40- to 128-bit programmable key
— Message digest execution unit (MDEU)
– SHA with 160-, 224-, or 256-bit message digest
– MD5 with 128-bit message digest
– HMAC with either algorithm
— Random number generator (RNG)
— Four crypto-channels, each supporting multi-command descriptor chains
– Static and/or dynamic assignment of crypto-execution units through an integrated controller
– Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
Universal serial bus (USB) dual role controller
— USB on-the-go mode with both device and host functionality
— Complies with USB specification Rev. 2.0
— Can operate as a stand-alone USB device
– One upstream facing port
– Six programmable USB endpoints
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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Overview
•
•
•
•
— Can operate as a stand-alone USB host controller
– USB root hub with one downstream-facing port
– Enhanced host controller interface (EHCI) compatible
– High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
— External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 133 MHz
— Eight chip selects for eight external slaves
— Up to eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
— Three protocol engines on a per chip select basis:
– General-purpose chip select machine (GPCM)
– Three user-programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
Programmable interrupt controller (PIC)
— Functional and programming compatibility with the MPC8260 interrupt controller
— Support for 8 external and 35 internal discrete interrupt sources
— Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
— Programmable highest priority request
— Four groups of interrupts with programmable priority
— External and internal interrupts directed to host processor
— Redirects interrupts to external INTA pin in core disable mode.
— Unique vector number for each interrupt source
Dual industry-standard I
2
C interfaces
— Two-wire interface
— Multiple master support
— Master or slave I
2
C mode support
— On-chip digital filtering rejects spikes on the bus
— System initialization data optionally loaded from I
2
C-1 EPROM by boot sequencer embedded
hardware
DMA controller
— Four independent virtual channels
— Concurrent execution across multiple channels with programmable bandwidth control
— Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
DMA_DACK[0:3], DMA_DDONE[0:3]
— All channels accessible to local core and remote PCI masters
MPC8343EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 11
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