Freescale Semiconductor
Technical Data
MPC866EC
Rev. 2, 2/2006
MPC866/MPC859
Hardware Specifications
This document contains detailed information on power
considerations, DC/AC electrical characteristics, and AC timing
specifications for the MPC866/859 family (refer to
Table 1
for a
list of devices). The MPC866P is the superset device of the
MPC866/859 family.This document describes pertinent electrical
and physical characteristics of the MPC8245. For functional
characteristics of the processor, refer to the
MPC866
PowerQUICC Family Users Manual
(MPC866UM/D).
Contents
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Maximum Tolerated Ratings . . . . . . . . . . . . . . . . . . . 8
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . 9
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Calculation and Measurement . . . . . . . . . . 12
Power Supply and Power Sequencing . . . . . . . . . . . 15
Layout Practices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Bus Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 16
IEEE 1149.1 Electrical Specifications . . . . . . . . . . . 46
CPM Electrical Characteristics . . . . . . . . . . . . . . . . . 48
UTOPIA AC Electrical Specifications . . . . . . . . . . . 72
FEC Electrical Characteristics . . . . . . . . . . . . . . . . . 74
Mechanical Data and Ordering Information . . . . . . . 78
Document Revision History . . . . . . . . . . . . . . . . . . . 93
1
Overview
The MPC866/859 is a derivative of Freescale’s MPC860
PowerQUICC™ family of devices. It is a versatile single-chip
integrated microprocessor and peripheral combination that can be
used in a variety of controller applications and communications
and networking systems. The MPC866/859/859DSL provides
enhanced ATM functionality over that of other ATM-enabled
members of the MPC860 family.
1.
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© Freescale Semiconductor, Inc., 2006. All rights reserved.
Features
Table 1
shows the functionality supported by the members of the MPC866/859 family.
2
Features
Table 1. MPC866 Family Functionality
Cache
Part
Instruction
MPC866P
MPC866T
MPC859P
MPC859T
MPC859DSL
MPC852T
3
1
Ethernet
SCC
Data
8 Kbytes
4 Kbytes
8 Kbytes
4 Kbytes
4 Kbytes
4 Kbytes
10T
Up to 4
Up to 4
1
1
1
2
10/100
1
1
1
1
1
1
4
4
1
1
1
1
2
2
2
2
2
1
2
1
SMC
16 Kbytes
4 Kbytes
16 Kbytes
4 Kbytes
4 Kbytes
4 KBytes
On the MPC859DSL, the SCC (SCC1) is for ethernet only. Also, the MPC859DSL does not support the Time Slot
Assigner (TSA).
2
On the MPC859DSL, the SMC (SMC1) is for UART only.
3
For more details on the MPC852T, please refer to the
MPC852T Hardware Specifications.
The following list summarizes the key MPC866/859 features:
•
Embedded single-issue, 32-bit PowerPC™ core (implementing the PowerPC architecture) with
thirty-two 32-bit general-purpose registers (GPRs)
— The core performs branch prediction with conditional prefetch, without conditional execution
— 4- or 8-Kbyte data cache and 4- or 16-Kbyte instruction cache (see
Table 1)
– 16-Kbyte instruction cache (MPC866P and MPC859P) is four-way, set-associative with 256 sets;
4-Kbyte instruction cache (MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative
with 128 sets.
– 8-Kbyte data cache (MPC866P and MPC859P) is two-way, set-associative with 256 sets; 4-Kbyte
data cache(MPC866T, MPC859T, and MPC859DSL) is two-way, set-associative with 128 sets.
– Cache coherency for both instruction and data caches is maintained on 128-bit (4-word) cache
blocks
– Caches are physically addressed, implement a least recently used (LRU) replacement algorithm, and
are lockable on a cache block basis.
— MMUs with 32-entry TLB, fully associative instruction and data TLBs
— MMUs support multiple page sizes of 4, 16, and 512 Kbytes, and 8 Mbytes; 16 virtual address spaces
and 16 protection groups.
— Advanced on-chip-emulation debug mode
The MPC866/859 provides enhanced ATM functionality over that of the MPC860SAR. The MPC866/859
adds major new features available in 'enhanced SAR' (ESAR) mode, including the following:
— Improved operation, administration, and maintenance (OAM) support
— OAM performance monitoring (PM) support
— Multiple APC priority levels available to support a range of traffic pace requirements
MPC866/MPC859 Hardware Specifications, Rev. 2
2
Freescale Semiconductor
•
Features
•
•
•
•
•
•
ATM port-to-port switching capability without the need for RAM-based microcode
Simultaneous MII (10/100Base-T) and UTOPIA (half-duplex) capability
Optional statistical cell counters per PHY
UTOPIA level 2 compliant interface with added FIFO buffering to reduce the total cell transmission
time. (The earlier UTOPIA level 1 specification is also supported.)
– Multi-PHY support on the MPC866, MPC859P, and MPC859T
– Four PHY support on the MPC866/859
— Parameter RAM for both SPI and I
2
C can be relocated without RAM-based microcode
— Supports full-duplex UTOPIA both master (ATM side) and slave (PHY side) operation using a 'split' bus
— AAL2/VBR functionality is ROM-resident.
Up to 32-bit data bus (dynamic bus sizing for 8, 16, and 32 bits)
Thirty-two address lines
Memory controller (eight banks)
— Contains complete dynamic RAM (DRAM) controller
— Each bank can be a chip select or RAS to support a DRAM bank
— Up to 30 wait states programmable per memory bank
— Glueless interface to page mode/EDO/SDRAM, SRAM, EPROMs, flash EPROMs, and other memory
devices.
— DRAM controller programmable to support most size and speed memory interfaces
— Four CAS lines, four WE lines, and one OE line
— Boot chip-select available at reset (options for 8-, 16-, or 32-bit memory)
— Variable block sizes (32 Kbytes–256 Mbytes)
— Selectable write protection
— On-chip bus arbitration logic
General-purpose timers
— Four 16-bit timers cascadable to be two 32-bit timers
— Gate mode can enable/disable counting
— Interrupt can be masked on reference match and event capture
Fast Ethernet controller (FEC)
— Simultaneous MII (10/100Base-T) and UTOPIA operation when using the UTOPIA multiplexed bus
System integration unit (SIU)
— Bus monitor
— Software watchdog
— Periodic interrupt timer (PIT)
— Low-power stop mode
— Clock synthesizer
— Decrementer and time base from the PowerPC architecture
— Reset controller
— IEEE 1149.1 test access port (JTAG)
—
—
—
—
MPC866/MPC859 Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Features
•
•
•
•
•
Interrupts
— Seven external interrupt request (IRQ) lines
— Twelve port pins with interrupt capability
— The MPC866P and MPC866T have 23 internal interrupt sources; the MPC859P, MPC859T, and
MPC859DSL have 20 internal interrupt sources.
— Programmable priority between SCCs (MPC866P and MPC866T)
— Programmable highest priority request
Communications processor module (CPM)
— RISC controller
— Communication-specific commands (for example,
GRACEFUL STOP TRANSMIT
,
ENTER HUNT MODE
, and
RESTART TRANSMIT
)
— Supports continuous mode transmission and reception on all serial channels
— Up to 8-Kbytes of dual-port RAM
— MPC866P and MPC866T have 16 serial DMA (SDMA) channels; MPC859P, MPC859T, and
MPC859DSL have 10 serial DMA (SDMA) channels.
— Three parallel I/O registers with open-drain capability
Four baud rate generators
— Independent (can be connected to any SCC or SMC)
— Allow changes during operation
— Autobaud support option
MPC866P and MPC866T have four SCCs (serial communication controller); MPC859P, MPC859T, and
MPC859DSL have one SCC; and SCC1 on MPC859DSL supports Ethernet only.
— Serial ATM capability on all SCCs
— Optional UTOPIA port on SCC4
— Ethernet/IEEE 802.3 optional on SCC1–4, supporting full 10-Mbps operation
— HDLC/SDLC
— HDLC bus (implements an HDLC-based local area network (LAN))
— Asynchronous HDLC to support PPP (point-to-point protocol)
— AppleTalk
— Universal asynchronous receiver transmitter (UART)
— Synchronous UART
— Serial infrared (IrDA)
— Binary synchronous communication (BISYNC)
— Totally transparent (bit streams)
— Totally transparent (frame based with optional cyclic redundancy check (CRC)
Two SMCs (serial management channels) (MPC859DSL has one SMC (SMC1) for UART.)
— UART
— Transparent
— General circuit interface (GCI) controller
— Can be connected to the time-division multiplexed (TDM) channels
MPC866/MPC859 Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Features
•
•
•
•
•
•
•
•
•
•
One serial peripheral interface (SPI)
— Supports master and slave modes
— Supports multiple-master operation on the same bus
One inter-integrated circuit (I
2
C) port
— Supports master and slave modes
— Multiple-master environment support
Time slot assigner (TSA) (MPC859DSL does not have TSA.)
— Allows SCCs and SMCs to run in multiplexed and/or non-multiplexed operation
— Supports T1, CEPT, PCM highway, ISDN basic rate, ISDN primary rate, user-defined
— 1- or 8-bit resolution
— Allows independent transmit and receive routing, frame synchronization, and clocking
— Allows dynamic changes
— On MPC866P and MPC866T, can be internally connected to six serial channels (four SCCs and two
SMCs); on MPC859P and MPC859T, can be connected to three serial channels (one SCC and two
SMCs).
Parallel interface port (PIP)
— Centronics interface support
— Supports fast connection between compatible ports on MPC866/859 or MC68360
PCMCIA interface
— Master (socket) interface, compliant with PCI Local Bus Specification (Rev 2.1)
— Supports one or two PCMCIA sockets whether ESAR functionality is enabled
— Eight memory or I/O windows supported
Debug interface
— Eight comparators: four operate on instruction address, two operate on data address, and two operate on
data.
— Supports conditions: =
≠
< >
— Each watchpoint can generate a breakpoint internally
Normal high and normal low power modes to conserve power
1.8 V core and 3.3 V I/O operation with 5-V TTL compatibility; refer to
Table 6
for a listing of the 5-V
tolerant pins.
357-pin plastic ball grid array (PBGA) package
Operation up to 133 MHz
MPC866/MPC859 Hardware Specifications, Rev. 2
Freescale Semiconductor
5
