QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1525
12/14 BIT, 25 TO 125 MSPS QUAD ADC
LTC2175-14, LTC2175-12, LTC2174-14, LTC2174-12, LTC2173-14, LTC2173-12, LTC2172-14,
LTC2172-12, LTC2171-14, LTC2171-12, LTC2170-14, LTC2170-12
DESCRIPTION
Demonstration circuit 1525 supports a family of 14/12
BIT 125 MSPS ADCs. Each assembly features one of
the following devices:
LTC2175-14, LTC2175-12,
LTC2174-14, LTC2174-12, LTC2173-14, LTC2173-12,
LTC2172-14, LTC2172-12, LTC2171-14, LTC2171-12,
LTC2170-14, LTC2170-12 high speed, quad ADCs.
The versions of the 1525A demo board are listed in
Table 1. Depending on the required resolution and
sample rate, the DC1525 is supplied with the appropri-
ate ADC. The circuitry on the analog inputs is opti-
mized for analog input frequencies from 5 MHz to
140MHz. Refer to the datasheet for proper input net-
works for different input frequencies.
Design files for this circuit board are available. Call
the LTC factory.
LTC is a trademark of Linear Technology Corporation
Table 1.
DC1525 Variants
ADC PART
NUMBER
RESOLUTION*
MAXIMUM SAMPLE
RATE
INPUT FREQUENCY
DC1525
VARIANTS
1525A-A
1525A-B
1525A-C
1525A-D
1525A-E
1525A-F
1525A-G
1525A-H
1525A-I
1525A-J
1525A-K
1525A-L
LTC2175-14
LTC2174-14
LTC2173-14
LTC2172-14
LTC2171-14
LTC2170-14
LTC2175-12
LTC2174-12
LTC2173-12
LTC2172-12
LTC2171-12
LTC2170-12
14-BIT
14-BIT
14-BIT
14-BIT
14-BIT
14-BIT
12-BIT
12-BIT
12-BIT
12-BIT
12-BIT
12-BIT
125 Msps
105 Msps
80 Msps
65 Msps
40 Msps
25 Msps
125 Msps
105 Msps
80 Msps
65 Msps
40 Msps
25 Msps
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
5MHz-140MHz
1
QUICK START GUIDE FOR DEMONSTRATION CIRCUIT 1525
12/14 BIT, 25 TO 125 MSPS QUAD ADC
Table 2.
Performance Summary (T
A
= 25°
C)
CONDITION
Depending on sampling rate and the A/D converter
provided, this supply must provide up to 500mA.
Depending on SENSE Pin Voltage
Minimum Logic High
Maximum Logic Low
Logic Output Voltages (differential)
Nominal Logic levels (100Ω load, 3.5mA Mode)
Minimum Logic levels (100Ω load, 3.5mA Mode)
Sampling Frequency (Convert Clock Fre-
quency)
Encode Clock Level
Encode Clock Level
Resolution
Input frequency range
SFDR
SNR
See Table 1
Single ended Encode Mode (ENC- tied to GND)
Differential Encode Mode (ENC- not tied to GND)
See Table 1
See Table 1
See Applicable Data Sheet
See Applicable Data Sheet
0-3.6V
0.2V-3.6V
VALUE
Optimized for 3V
[3V
6.0V min/max]
PARAMETER
Supply Voltage – DC1525A
Analog input range
Logic Input Voltages
1 V
PP
to 2V
PP
1.3V
0.6V
350mV/1.25V common mode
247mV/1.25V common mode
QUICK START PROCEDURE
Demonstration circuit 1525 is easy to set up to
evaluate the performance of the LTC2175 A/D
converters. Refer to Figure 1 for proper meas-
urement equipment setup and follow the proce-
dure below:
SETUP
If a DC1371 “PStache” Data Acquisition and Col- Start Guide to install the required software and
lection System was supplied with the DC1525 for connecting the DC1371 to the DC1525 and to
demonstration circuit, follow the DC1371 Quick a PC running Windows 2000 or XP.
2
3.5-6V
To provided power supply
+
Parallel/Serial
Analog Inputs
Channel 1
Channel 2
Use provided USB cable
Channel 3
Channel 4
Single Ended
Encode Clock.
Use provided
DC1075
Figure 1. DC1525 Setup (zoom for detail)
3
DC1525 DEMONSTRATION CIRCUIT
BOARD JUMPERS
The DC1525 demonstration circuit board
should have the following jumper settings as
default positions: (as per Figure 1)
J13: PAR/SER : Selects Parallel or Serial pro-
gramming mode. (Default - Serial)
Optional Jumpers:
J8: Term: Enables/ Disable optional output
termination. (Default - Removed)
J5: ILVDS: Selects either 1.75mA or 3.5mA
of output current for the LVDS drivers. (De-
fault – Removed)
APPLYING POWER AND SIGNALS TO THE
DC1525 DEMONSTRATION CIRCUIT
The DC1371 is used to acquire data from the
DC1525, the DC1371 must FIRST be con-
nected to a powered USB port and have =5V
applied power BEFORE applying +3.6V to
+6.0V across the pins marked “V+” and
“GND” on the DC1525. DC1525 requires 3.6V
for proper operation.
J14: LANE: Selects either 1 lane or 2 lane
output modes (Default – Removed) NOTE:
The DC1371 does not support 1 lane opera-
tion.
J15:
SHDN: Enables and disables the
LTC2175. (Default - Removed)
J2: WP: Enable/Disables write protect for the
EEPROM. (Default – Removed)
Note: optional jumper should be left open to
ensure proper serial configuration.
Regulators on the board produce the volt-
ages required for the ADC. The DC1525
demonstration circuit requires up to 500mA
depending on the sampling rate and the A/D
converter supplied.
The DC1525 should not be removed, or con-
nected to the DC1371 while power is applied.
ANALOG INPUT NETWORK
For optimal distortion and noise performance
the RC network on the analog inputs may
need to be optimized for different analog input
frequencies. For input frequencies above 140
MHz, refer to the LTC2175 datasheet for a
proper input network. Other input networks
may be more appropriate for input frequen-
cies less that 5MHz.
In almost all cases, filters will be required on
both analog input and encode clock to provide
data sheet SNR.
The filters should be located close to the in-
puts to avoid reflections from impedance dis-
continuities at the driven end of a long trans-
mission line. Most filters do not present 50Ω
outside the passband. In some cases, 3dB to
10dB pads may be required to obtain low dis-
tortion.
If your generator cannot deliver full scale sig-
nals without distortion, you may benefit from a
medium power amplifier based on a Gallium
Arsenide Gain block prior to the final filter.
This is particularly true at higher frequencies
where IC based operational amplifiers may be
unable to deliver the combination of low noise
figure and High IP3 point required. A high or-
der filter can be used prior to this final ampli-
4
fier, and a relatively lower Q filter used be-
tween the amplifier and the demo circuit.
Apply the analog input signal of interest to the
SMA connectors on the DC1525 demonstra-
tion circuit board marked “J3 AIN1”, “J4 AIN2”,
“J6 AIN3”, “J7 AIN4”. These inputs corre-
spond with channels 1-4 of the ADC respec-
tively. These inputs are capacitive coupled to
Balun transformers ETC1-1-13.
connector follows the VITA-57/FMC standard,
but all signals should be verified when using an
FMC carrier card other than the DC1371.
SOFTWARE
The DC1371A is controlled by the PScope
System Software provided or downloaded
from the Linear Technology website at
http://www.linear.com/software/.
To start the data collection software if
“PScope.exe”, is installed (by default) in
\Program Files\LTC\PScope\, double click the
PScope Icon or bring up the run window un-
der the start menu and browse to the PScope
directory and select PScope.
If the DC1525 demonstration circuit is prop-
erly connected to the DC1371, PSCOPE
should automatically detect the DC1525, and
configure itself accordingly.
If everything is hooked up properly, powered
and a suitable convert clock is present, click-
ing the “Collect” button should result in time
and frequency plots displayed in the PScope
window. Additional information and help for
PScope is available in the DC1371A Quick
Start Guide and in the online help available
within the PScope program itself.
ENCODE CLOCK
NOTE:
Apply an encode clock to the SMA
connector on the DC1525 demonstration cir-
cuit board marked “J11 CLK+”. As a default
the DC1525 is populated to have a single
ended input.
For the best noise performance, the ENCODE
INPUT must be driven with a very low jitter,
square wave source. The amplitude should be
large, up to 3V
P-P
or 13dBm. When using a
sinusoidal signal generator a squaring circuit
can be used. Linear Technology also pro-
vides demo board DC1075A that divides a
high frequency sine wave by four, producing a
low jitter square wave for best results with the
LTC2175.
Using band pass filters on the clock and the
analog input will improve the noise perform-
ance by reducing the wideband noise power
of the signals. In the case of the DC1525 a
band pass filter used for the clock should be
used prior to the DC1075A. Datasheet FFT
plots are taken with 10 pole LC filters made by
TTE (Los Angeles, CA) to suppress signal
generator harmonics, non-harmonically re-
lated spurs and broadband noise. Low phase
noise Agilent 8644B generators are used for
both the Clock input and the Analog input.
DIGITAL OUTPUTS
Data outputs. data clock, and frame clock sig-
nals are available on J1 of the DC1525. This
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