Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................ -60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) ................................. +300°C
Soldering Temperature (reflow) .......................................+260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
(V
DD
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
DD
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz external clock (50% duty cycle), V
REF
= 2.5V (MAX11627//MAX11629/MAX11633); V
REF
= 4.096V
(MAX11626/MAX11628/MAX11632), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
DC ACCURACY (Note 1)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error
Offset Error Temperature
Coefficient
Gain Temperature Coefficient
Channel-to-Channel Offset
Matching
DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, f
SCLK
= 4.8MHz)
Signal-to-Noise Plus Distortion
SINAD
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
Up to the 5th
harmonic
MAX11627/MAX11629/
MAX11633
MAX11626/MAX11628/
MAX11632
71
73
-80
dBc
-88
81
89
76
1
100
dBc
dBc
MHz
kHz
dB
(Note 2)
RES
INL
DNL
No missing codes over temperature
±0.5
±0.5
±2
±0.8
±0.1
12
±1.0
±1.0
±4.0
±4.0
Bits
LSB
LSB
LSB
LSB
ppm/°C
FSR
ppm/°C
LSB
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Total Harmonic Distortion
THD
Spurious-Free Dynamic Range
Intermodulation Distortion
Full-Power Bandwidth
Full-Linear Bandwidth
SFDR
IMD
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
f
IN1
= 29.9kHz, f
IN2
= 30.2kHz
-3dB point
S/(N + D) > 68dB
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MAX11626–MAX11629/
MAX11632/MAX11633
Electrical Characteristics (continued)
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
(V
DD
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
DD
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz external clock (50% duty cycle), V
REF
= 2.5V (MAX11627//MAX11629/MAX11633); V
REF
= 4.096V
(MAX11626/MAX11628/MAX11632), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
CONVERSION RATE
Power-Up Time
Acquisition Time
Conversion Time
External Clock Frequency
Aperture Delay
Aperture Jitter
ANALOG INPUT
Input Voltage Range
Input Leakage Current
Input Capacitance
INTERNAL REFERENCE
REF Output Voltage
REF Temperature Coefficient
Output Resistance
REF Output Noise
REF Power-Supply Rejection
EXTERNAL REFERENCE INPUT
REF Input Voltage Range
V
REF
V
REF
= 2.5V (MAX11627/MAX11629/
MAX11633); V
REF
= 4.096V
(MAX11626/MAX11628/MAX11632),
f
SAMPLE
= 300ksps
V
REF
= 2.5V (MAX11627/MAX11629/
MAX11633); V
REF
= 4.096V
(MAX11626/MAX11628/MAX11632),
f
SAMPLE
= 0
1.0
V
DD
+ 50mV
40
100
µA
±0.1
±5
V
PSRR
TC
REF
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
4.024
2.48
4.096
2.50
±20
±30
6.5
200
-70
4.168
2.52
V
ppm/°C
kΩ
µVRMS
dB
Unipolar
V
IN
= V
DD
During acquisition time (Note 5)
0
±0.01
24
V
REF
±1
V
µA
pF
t
PU
t
ACQ
t
CONV
f
SCLK
Internally clocked
Externally clocked (Note 4)
Externally clocked conversion
Data I/O
30
< 50
2.7
0.1
4.8
10
External reference
Internal reference (Note 3)
0.6
3.5
0.8
65
µs
µs
µs
MHz
ns
ps
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REF Input Current
I
REF
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MAX11626–MAX11629/
MAX11632/MAX11633
Electrical Characteristics (continued)
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
(V
DD
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
DD
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632), f
SAMPLE
= 300kHz, f
SCLK
= 4.8MHz external clock (50% duty cycle), V
REF
= 2.5V (MAX11627//MAX11629/MAX11633); V
REF
= 4.096V
(MAX11626/MAX11628/MAX11632), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
DIGITAL INPUTS (SCLK, DIN,
CS, CNVST)(Note
6)
Input Voltage Low
Input Voltage High
Input Hysteresis
Input Leakage Current
Input Capacitance
DIGITAL OUTPUTS (DOUT,
EOC)
Output Voltage Low
Output Voltage High
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
Supply Voltage
V
DD
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
Internal
reference
External
reference
Internal
reference
External
reference
PSR
f
SAMPLE
= 300ksps
f
SAMPLE
= 0, REF on
Shutdown
f
SAMPLE
= 300ksps
Shutdown
f
SAMPLE
= 300ksps
f
SAMPLE
= 0, REF on
Shutdown
f
SAMPLE
= 300ksps
Shutdown
4.75
2.7
1750
1000
0.2
1050
0.2
2300
1050
0.2
1550
0.2
±0.2
±0.2
5.25
3.6
2000
1200
5
1200
5
2550
1350
5
1700
5
±1
±1.4
mV
µA
µA
V
V
IL
V
IH
V
HYST
I
IN
C
IN
I
SINK
= 2mA
I
SINK
= 4mA
I
SOURCE
= 1.5mA
CS
= V
DD
CS
= V
DD
V
DD
- 0.5
±0.05
15
±1
V
IN
= 0V or V
DD
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
0.8
V
DD
x 0.3
2.0
V
DD
x 0.7
200
±0.01
15
0.4
0.8
±1.0
UNITS
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
MAX11626/MAX11628/MAX11632
MAX11627/MAX11629/MAX11633
V
V
mV
µA
pF
V
OL
V
OH
I
L
C
OUT
V
V
µA
pF
MAX11627/MAX11629/MAX11633
Supply Current (Note 7)
I
DD
MAX11626/MAX11628/MAX11632
Supply Current (Note 7)
IDD
Power-Supply Rejection
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
V
DD
= 2.7V to 3.6V; full-scale input
V
DD
= 4.75V to 5.25V; full-scale input
MAX11627/MAX11629/MAX11633 tested at V
DD
= +3V. MAX11626/MAX11628/MAX11632 tested at V
DD
= +5V.
Offset nulled.
Time for reference to power up and settle to within 1 LSB.
Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the
Typical Operating
Characteristics
section.
Note 6:
When
CNVST
is configured as a digital input, do not apply a voltage between V
IL
and V
IH
.
Note 7:
Supply current is specified depending on whether an internal or external reference is used for voltage conversions.
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MAX11626–MAX11629/
MAX11632/MAX11633
Timing Characteristics (Figure 1)
12-Bit, 300ksps ADCs
with FIFO and Internal Reference
(V
DD
= +2.7V to +3.6V (MAX11627/MAX11629/MAX11633); V
DD
= +4.75V to +5.25V (MAX11626/MAX11628/MAX11632),
f
SAMPLE
=300kHz, f
SCLK
= 4.8MHz (50% duty cycle), V
REF
= 2.5V (MAX11627//MAX11629/MAX11633); V
REF
= 4.096V (MAX11626/
MAX11628/MAX11632), T
A
= T
MIN
to T
MAX
, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SCLK Clock Period
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to DOUT Transition
CS
Rise to DOUT Disable
CS
Fall to DOUT Enable
DIN to SCLK Rise Setup
SCLK Rise to DIN Hold
CS
Low to SCLK Setup
CS
High to SCLK Setup
CS
High After SCLK Hold
CS
Low After SCLK Hold
CNVST
Pulse Width Low
CS
or
CNVST
Rise to
EOC
Low (Note 8)
SYMBOL
t
CP
t
CH
t
CL
t
DOT
t
DOD
t
DOE
t
DS
t
DH
t
CSS0
t
CSS1
t
CSH1
t
CSH0
t
CSPW
CKSEL = 00
CKSEL = 01
Voltage conversion
Reference power-up
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
40
0
40
40
0
0
40
1.4
7
65
4
Data I/O
CONDITIONS
Externally clocked conversion
MIN
208
100
40
40
40
40
40
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
µs
µs
Note 8:
This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal refer-
ence needs to be powered up, the total time is additive.
Typical Operating Characteristics
V
DD
= +5V, V
REF
= +4.096V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C, for MAX11626/MAX11628/MAX11632, unless otherwise noted.
V
DD
= +3V, V
REF
= +2.5V, f
SCLK
= 4.8MHz, C
LOAD
= 30pF, T
A
= +25°C, for MAX11627/MAX11629/MAX11633, unless otherwise noted.
