19-4506; Rev 4; 2/97
UAL
IT MAN
TION K
A
SHEET
EVALU
S DATA
W
FOLLO
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
General Description
____________________________Features
o
o
o
o
o
12-Bit Resolution, 1/2LSB Linearity
+5V or ±5V Operation
Built-In Track/Hold
Internal Reference with Adjustment Capability
Low Power: 3mA Operating Mode
20µA Power-Down Mode
o
100ksps Tested Sampling Rate
o
Serial and 8-Bit Parallel µP Interface
o
24-Pin Narrow DIP and Wide SO Packages
MAX191
The MAX191 is a monolithic, CMOS, 12-bit analog-to-
digital converter (ADC) featuring differential inputs,
track/hold (T/H), internal voltage reference, internal or
external clock, and parallel or serial µP interface. The
MAX191 has a 7.5µs conversion time, a 2µs acquisition
time, and a guaranteed 100ksps sample rate.
The MAX191 operates from a single +5V supply or from
dual ±5V supplies, allowing ground-referenced bipolar
input signals. The device features a logic power-down
input, which reduces the 3mA V
DD
supply current to
50µA max, including the internal-reference current.
Decoupling capacitors are the only external compo-
nents needed for the power supply and reference. This
ADC operates with either an external reference, or an
internal reference that features an adjustment input for
trimming system gain errors.
The MAX191 provides three interface modes: two 8-bit
parallel modes, and a serial interface mode that is com-
patible with SPI
TM
, QSPI
TM
, and MICROWIRE
TM
serial-
interface standards.
Ordering Information
PART
MAX191ACNG
MAX191BCNG
MAX191ACWG
MAX191BCWG
MAX191BC/D
MAX191AENG
MAX191BENG
MAX191AEWG
MAX191BEWG
MAX191AMRG
MAX191BMRG
TEMP. RANGE
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-55°C to +125°C
-55°C to +125°C
PIN-PACKAGE
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
24 Wide SO
Dice*
24 Narrow Plastic DIP
24 Narrow Plastic DIP
24 Wide SO
24 Wide SO
24 Narrow CERDIP**
24 Narrow CERDIP**
ERROR
(LSB)
±1/2
±1
±1/2
±1
±1
±1/2
±1
±1/2
±1
±1/2
±1
________________________Applications
Battery-Powered Data Logging
PC Pen Digitizers
High-Accuracy Process Control
Electromechanical Systems
Data-Acquisition Boards for PCs
Automatic Testing Systems
Telecommunications
Digital Signal Processing (DSP)
* Dice are specified at T
A
= +25°C, DC parameters only.
** Contact factory for availability and processing to MIL-STD-883.
Pin Configuration
TOP VIEW
PD
1
24
V
DD
23
CLK/SCLK
22
PAR
21
HBEN
Functional Diagram
V
DD
24
5
VREF
6
REFADJ
CLK/SCLK
23
OSC
3-STATE
OUTPUT
8-BIT
BUS
AND
SERIAL
I/O
18
17
16
15
14
13
11
10
D7/DOUT
D6/SCLK
OUT
D5/SSTRB
D4
D3/D11
D2/D10
D1/D9
D0/D8
V
SS
2
AIN+
3
AIN-
4
VREF
5
REFADJ
6
AGND
7
BIP
8
BUSY
9
MAX191
20
CS
19
RD
18
D7/DOUT
17
D6/SCLK
OUT
16
D5/SSTRB
15
D4
14
D3/D11
13
D2/D10
2.46V
REF
12
AIN +
AIN -
3
4
MAX191
7
AGND
12
DGND
IN REF OUT
12-BIT
SAR ADC
2
V
SS
CONTROL
LOGIC
1 22 8
BIP
PD
PAR
20
19
9
21
CS
RD
BUSY
HBEN
D0/D8
10
D1/D9
11
DGND
12
DIP/SO
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
MAX191
ABSOLUTE MAXIMUM RATINGS
V
DD
to DGND............................................................-0.3V to +7V
V
SS
to AGND ............................................................-7V to +0.3V
V
DD
to V
SS
..............................................................................12V
AGND, VREF, REFADJ to DGND................-0.3V to (V
DD
+ 0.3V)
AIN+, AIN-,
PD
to V
SS
.................................-0.3V to (V
DD
+ 0.3V)
CS, RD,
CLK, BIP, HBEN, PAR, to DGND....-0.3V to (V
DD
+ 0.3V)
BUSY,
D0–D7 to DGND..............................-0.3V to (V
DD
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
Narrow Plastic DIP (derate 13.33mW/°C above +70°C)....1067mW
Wide SO (derate 11.76mW/°C above +70°C) ......................941mW
Narrow CERDIP (derate 12.50mW/°C above +70°C) ........1000mW
Operating Temperature Ranges
MAX191_C_ _ ................................................................0°C to +70°C
MAX191_E_ _ .............................................................-40°C to +85°C
MAX191_M_ _ ..........................................................-55°C to +125°C
Storage Temperature Range.....................................-65°C to +160°C
Lead Temperature (soldering, 10sec).....................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 5V ±5%, V
SS
= 0V or -5V ±5%, f
CLK
= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
DC ACCURACY
(Note 2)
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Gain Error (Note 3)
Gain-Error Tempco (Note 4)
Signal-to-Noise plus Distortion
Ratio
Total Harmonic Distortion
(up to the 5th Harmonic)
Spurious-Free Dynamic Range
CONVERSION RATE
Conversion Time (Note 5)
Track/Hold Acquisition Time
Aperture Delay
Aperture Jitter
External Clock Frequency
Range (Note 6)
f
CLK
0.1
25
50
1.6
t
CONV
Synchronous CLK (12 to 13 CLKs)
Internal CLK, C
L
= 120pF
7.50
6
12
8.125
18
2
µs
µs
ns
ps
MHz
INL
DNL
MAX191A
MAX191B
No missing codes over temperature
MAX191A
MAX191B
MAX191A
MAX191B
Excludes internal-reference drift
±0.2
12
±1/2
±1
±1
±1
±2
±2
±3
Bits
LSB
LSB
LSB
LSB
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DYNAMIC ACCURACY
(sample rate = 100kHz, V
IN
= 4Vp-p)
SINAD
THD
SFDR
1kHz input signal, T
A
= +25°C
1kHz input signal, T
A
= +25°C
1kHz input signal, T
A
= +25°C
80
70
-80
dB
dB
dB
2
_______________________________________________________________________________________
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%, V
SS
= 0V or -5V ±5%, f
CLK
= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
ANALOG INPUT
Input Voltage Range (Note 7)
Input Leakage Current
Input Capacitance (Note 6)
Small-Signal Bandwidth
INTERNAL REFERENCE
VREF Output Voltage
VREF Output Tempco (Note 8)
Output Current Capability (Note 9)
Load Regulation
Output Short-Circuit Current
Capacitive Load Required
Power-Supply Rejection
REFADJ Input Adjustment Range
(Note 10)
REFADJ Disable Threshold
REFADJ Output Voltage
REFADJ Input Current
REFERENCE INPUT
Input Voltage Range
Input Current
Input Resistance
LOGIC INPUTS
Input Low Voltage
Input High Voltage
Input Current
Input Current CLK
Input Capacitance (Note 6)
PD
Input Low Voltage
PD
Input High Voltage
PD
Input Current
PD
External Leakage for Float
State (Note 12)
PD
Floating-State Voltage
V
FLT
V
IL
V
IH
I
IN
I
IN
C
IN
V
IL
V
IH
I
IN
PD
= 0V to V
DD
(Note 11)
Maximum current allowed for “floating state”
Reference compensation mode—external
2.8
4.5
±20
±100
CS, RD,
CLK, HBEN, PAR, BIP
CS, RD,
CLK, HBEN, PAR, BIP
V
IN
= 0V to V
DD
PD
= high/float
PD
= low
±0.1
10
0.5
2.4
±10
±200
0.8
V
V
µA
µA
pF
V
V
µA
nA
V
External-reference mode
External-reference = 5V
External-reference mode
5
10
2.5
5.0
1
V
mA
kΩ
REFADJ = 5V
Reference compensation mode—external
V
DD
= ±5%, V
SS
= ±5%
4.7
±300
-60
4.5
2.4
60
30
T
A
= +25°C
MAX191_C
MAX191_E
MAX191_M
T
A
= +25°C
T
A
= +25°C, I
OUT
= 0mA to 2mA
18
4.076
4.096
4.116
50
60
80
2
4
mA
mV
mA
µF
µV
mV
V
V
µA
V
mA
ppm/°C
V
IN
= V
SS
to V
DD
45
2
V
SS
V
DD
±10
80
V
µA
pF
MHz
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MAX191
_______________________________________________________________________________________
3
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
MAX191
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%, V
SS
= 0V or -5V ±5%, f
CLK
= 1.6MHz, 50% duty cycle, AIN- = AGND, BIP = 0V, slow-memory mode, internal-reference
mode, reference compensation mode—external, synchronous operation, Figure 6, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 1)
PARAMETER
LOGIC OUTPUTS
Output Low Voltage
Output High Voltage
Three-State Leakage Current
Three-State Output
Capacitance (Note 6)
POWER REQUIREMENTS
Positive Supply Voltage
Negative Supply Voltage
Positive Supply Current
Negative Supply Current
Positive Supply Rejection (Note 13)
Negative Supply Rejection (Note 13)
V
DD
V
SS
I
DD
I
SS
CS =
RD
= V
DD
,
AIN = 5V, D0/D8–D7/
DOUT = 0V or V
DD
,
HBEN = PAR = BIP
= 0V or V
DD
PD
= high/float
PD
= low
PD
= high/float
PD
= low
4.75
-5.25
3
20
20
1
5.25
0
5
50
100
20
±1/2
±1/2
V
V
mA
µA
µA
LSB
LSB
V
OL
V
OH
I
L
C
OUT
I
OUT
= 1.6mA
I
OUT
= -200µA
D0/D8-D7/DOUT
4.0
±10
15
0.4
V
V
µA
pF
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FS change, V
DD
= 5V ±5%
FS change, V
SS
= -5V ±5%
TIMING CHARACTERISTICS (Figures 6–10)
(V
DD
=5V ±5%, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 14)
PARAMETER
CS
to
RD
Setup Time
RD
to
BUSY
Delay
Data Access Time (Note 15)
RD
Pulse Width
CS
to
RD
Hold Time
Data Setup Time After
BUSY
(Note 15)
Bus-Relinquish Time (Note 16)
HBEN to
RD
Setup Time
HBEN to
RD
Hold Time
Delay Between Read
Operations (Note 6)
Delay Between Conversions
Aperture Delay
CLK to
BUSY
Delay (Note 6)
SCLK
OUT
to SSTRB
Rise Delay
SCLK
OUT
to SSTRB
Fall Delay
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
Jitter < 50ps
80
0
200
2
25
200
100
100
230
130
130
260
150
150
C
L
= 50pF
C
L
= 100pF
150
0
80
100
100
0
200
2
CONDITIONS
T
A
= +25°C
MIN TYP MAX
0
120
120
150
0
100
110
120
0
200
2
MAX191C/E
MIN TYP MAX
0
140
140
150
0
120
120
MAX191M
MIN TYP MAX
0
160
160
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
ns
4
_______________________________________________________________________________________
Low-Power, 12-Bit Sampling ADC
with Internal Reference and Power-Down
TIMING CHARACTERISTICS (Figures 6–10) (continued)
(V
DD
=5V ±5%, V
SS
= 0V or -5V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.) (Note 14)
PARAMETER
CS
or
RD
Hold Time
CS
or
RD
Setup Time
CS
to DOUT Three-State
SCLK to SCLK
OUT
Delay
SCLK
OUT
to DOUT Delay
SCLK to DOUT Delay
SCLK to SSTRB Delay
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
SYMBOL
t
16
t
17
t
19
t
20
t
21
t
22
t
23
CONDITIONS
T
A
= +25°C
MIN TYP MAX
10
150
100
160
100
240
260
MAX191C/E
MIN TYP MAX
10
150
110
180
130
260
310
MAX191M
MIN TYP MAX
10
150
120
200
150
280
350
UNITS
ns
ns
ns
ns
ns
ns
ns
MAX191
Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
V
DD
= 5V, V
SS
= 0V, FS = VREF.
FS = VREF, offset nulled, ideal last-code transition = FS - 3/2 LSB.
Gain-Error Tempco =
∆GE
is the gain-error change from T
A
= +25°C to T
MIN
or T
MAX
.
Conversion time defined as the number of clock cycles times the clock period; clock has a 50% duty cycle.
Guaranteed by design, not production tested.
AIN+, AIN- must not exceed supplies for specified accuracy.
VREF TC =
∆T,
where
∆VREF
is reference-voltage change from T
A
= +25°C to T
MIN
or T
MAX
.
Output current should not change during conversion. This current is in addition to the current required by the internal DAC.
REFADJ adjustment range is defined as the allowed voltage excursion on REFADJ relative to its unadjusted value of 2.4V.
This will typically result in a 1.7 times larger change in the REF output (Figure 19a).
This current is included in the
PD
supply current specification.
Floating the
PD
pin guarantees external compensation mode.
V
REF
= 4.096V, external reference.
All input control signals are specified with t
r
= t
f
= 5ns (10% to 90% of 5V) and timed from a voltage level of 1.6V.
t
3
and t
6
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
t
7
is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
_______________________________________________________________________________________
5
FPGA/CPLD
