FUJITSU SEMICONDUCTOR
MB91F467BA/466BA/465BA/464BA
preliminary datasheet
MB91460 series
European MCU Design Centre (EMDC)
Fujitsu Microelectronics Europe GmbH
Pittlerstr. 47
63225 Langen, Germany
Fujitsu and
Fujitsu Microelectronics Solutions Limited(FMSL)
Version
0.27,
File: mb91f467ba_shortspec_r2.0.doc
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
Revision History
Version
0.10
0.11
0.12
0.13
Date
2005-09-01
2005-09-04
2006-01-20
2006-01-25
Remark
Initial draft
Memory map + flash memory map updated
Addition of external bus interface option
Corrections for external bus interface option;
Remove of package information: MB91F467BA will be delivered
in a QFP-144 package with pure Sn pin plating, the related
package number is to be defined
Use UART3 instead of UART2
Upgrade tables and feature lists to refer to external bus interface
option
Updated pinning, added 1 USART in non-external-bus mode,
exchanged WRX[1] against WRX[0]
Changed pinning for 6ch CAN, 32ch ADC and NMI
Corrected operation supply voltage range
Delete
“ESD
Protection” of Electrical Characteristics
Added condition of current consumption
Add a postscript to
“function
limitation” in
“2.1.Overview
Table”
Add the
“6.
IO Map”
1.1.Block Diagram change IO Voltage
2.2.1.Memory Map change
“not
available area”
2.2.7.&2.2.8. correct memory capacity.
2.3. correct feature of
“Clock
supervisor”
6. Add a postscript to
“function
limitation”
Add a Cancellation line
“D/A
Converter”,”Interrupt Control Unit”
and
“CAN
0-5 Status Flags”
4. Added
“Type”
in Table
6. Del a Cancellation line
”Interrupt
Control Unit”
Add a Cancellation line Test function
(C-Unit Test,
“CSVCR(bit7)”,”CANCKD”and”I-Unit
Test)
6. Del a postscript(*4) It was already descripted
“User’s
Manual”.
Added MB91F465BA information
“A
Cover” & 1 & 4.1 & 4.2.1 & 4.2.2 Add
“MB91F465BA”
1.1 & 2.1 Add 544KB FLASH and explanation of FLASH
2.2.1
Add memory map of MB91F465BA
2.2.9
Add 544KB Fash memory map
6
Add Flash area of MB91F465BA
Changed a discription about Clock supervisor
2.3 Clock supervisor function revival
Added
“4.3
I/O Pin Types”
0.14
0.15
0.16
0.17
0.18
0.19
0.20
2006-02-14
2006-02-16
2006-03-08
2006-03-09
2006-06-08
2006-07-20
2006-07-25
2006-08-07
0.21
2006-08-08
2007-03-12
0.22
2007-04-09
Page 2 of 125
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
0.23
2007-04-12
2007-04-19
2007-05-01
0.24
2007-05-30
0.25
2007-06-18
0.26
2007-07-24
Added MB91F466BA/MB91F464BA information
“A
Cover” & 1 & 4.1 & 4.2.1 & 4.2.2
Add
“MB91F466BA”
and”MB91F464BA
1.1 & 2.1 Add 832KB/416KB FLASH and explanation of FLASH
2.2.1
Add memory map of MB91F466BA/MB91F464BA
2.2.9
Add 832KB/416KB Fash memory map
6
Add Flash area of MB91F466BA/MB91F464BA
Change of Chapter Constitution and Addition of
“Recommended
Settings”
Chap1 Overview
(no change)
Chap2 Feature List
(small change in this Chap)
Chap3 Recommended Settings
(addition)
Chap4 IO Map
(Chap6 in a previous Ver.)
Chap5 Interrupt Vector Table
(Chap3 in a previous Ver.)
Chap6 Package and Pin Assignment (Chap4 in a previous Ver.)
Chap7 Electrical Characteristics
(Chap5 in a previous Ver.)
Addition of information to be related Flash
(From 2.4.1 to 2.4.4)
Added information of specification change about port function.
2.2.7 & 6.2.2 Add
“Limitation”
2.2.7
Add
“WRX1”
6.2.2
Change function of Pin44.
Changed a division point of IO power supply group
6.2.1 & 6.2.2
Added package dimension in
“6.1
Package”
Change of initial value in
“4
IO map”
LVSEL (04C4h) : 00000111 -> 00000101
REGSEL(04CEh) : 00000110 -> 00000100
Changed of initial value in
“4
IO map”
PFR00 (0D80h) : 00000000 -> 11111111
PFR01 (0D80h) : 00000000 -> 11111111
PFR02* (0D80h) : 00000000 -> 11111111
PFR03* (0D80h) : 00000000 -> 11111111
PFR04* (0D84h) : 00000000 -> 11111111
PFR05 (0D84h) :
. .
000000 ->
. .
111111
PFR06 (0D84h) : 00000000 -> 11111111
PFR07 (0D84h) : 00000000 -> 11111111
PFR08 (0D88h) : 0
. .0 . . .0
-> 1
. .1 . . .1
PFR09 (0D88h) :
. . . . . .
00 ->
. . . . . .
11
PFR10 (0D88h) :
. . . . . . .
0 ->
. . . . . . .
1
*
PFR02, PFR03, and PFR04 changed only the description.
Because it is a part that IO doesn't have.
0.27
2007-09-05
# 2.1
：
Changed
“Core”
and
“Resource”
frequency.
・Core
frequency 80 MHz / 100 MHz -> 96 MHz
・Resource
frequency 40 MHz / 50 MHz -> 48 MHz
# 2.2.2：Changed
maximum operating frequency and PLL clock
multiplier method.
・Core
clock =
“80
MHz /100 MHz” ->
“96
MHz”
・multiplied
by 20 -> multiplied by 24
Page 3 of 125
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
0.27
# 3.3
：
The combination description of
“CMPR
: 03E9” ,
“Baseclk
: 52MHz” and
“Fmax
: 96.9MHz” was deleted
from the table.
# 7.2
：Parameter
item in table :
The maximum frequency was changed from 100MHz to
96MHz about the frequency description of
“Lock-up
time
PLL1”.
Latest revision
Page 4 of 125
European MCU Design Centre
MB91F467BA/466BA/465BA/464BA preliminary datasheet ver. 0.27
Table of contents
1
2
Overview........................................................................................................................ 7
1.1
2.1
2.2
Block Diagram .......................................................................................................... 7
Overview Table......................................................................................................... 8
Core Functionality................................................................................................... 10
Memory Map .................................................................................................... 11
FR70 CPU Core............................................................................................... 13
Instruction Cache ............................................................................................. 13
Interrupt Controller ........................................................................................... 14
Internal Data RAM............................................................................................ 14
Internal Program/Data RAM ............................................................................. 14
External Bus Interface...................................................................................... 14
DMA Controller................................................................................................. 15
Feature List ................................................................................................................... 8
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.3
2.4
Peripheral Function ................................................................................................ 16
Embedded Program/Data Memory ......................................................................... 21
Flash features .................................................................................................. 21
CPU Mode ....................................................................................................... 22
Flash configuration in CPU mode .......................................................................................... 22
Flash access timing settings in CPU mode ............................................................................ 24
Address mapping from CPU to parallel programming mode.................................................... 25
2.4.1
2.4.2
2.4.2.1
2.4.2.2
2.4.2.3
2.4.3
2.4.3.1
2.4.3.2
Parallel flash programming mode..................................................................... 26
Flash configuration in parallel flash programming mode ......................................................... 26
Pin connections in parallel programming mode ...................................................................... 27
2.4.4
2.4.4.1
2.4.4.2
2.4.4.3
2.4.4.4
Flash Security .................................................................................................. 28
Vector addresses.................................................................................................................. 28
Security Vector FSV1............................................................................................................ 28
Security Vector FSV2............................................................................................................ 31
Register description for Flash Security................................................................................... 32
3
Recommended Settings ............................................................................................. 33
3.1
3.2
3.3
PLL and Clockgear settings.................................................................................... 33
Flash interface settings........................................................................................... 34
Clock Modulator settings ........................................................................................ 35
4
5
IO Map.......................................................................................................................... 39
Interrupt Vector Table................................................................................................101
Page 5 of 125
