Freescale Semiconductor
Technical Data
Document Number:
MC33395
Rev 4.0, 2/2007
Three-Phase Gate Driver IC
The 33395 simplifies the design of high-power BLDC motor control
design by combining the gate drive, charge pump, current sense, and
protection circuitry necessary to drive a three-phase bridge
configuration of six N-channel power MOSFETs. Mode logic is
incorporated to route a pulse width modulation (PWM) or a
complementary PWM output signal to either low-side or high-side
MOSFETs of the bridge.
Detection and drive circuitry are also incorporated to control a
reverse battery protection high-side MOSFET switch. PWM
frequencies up to 28 kHz are possible. Built-in protection circuitry
prevents damage to the MOSFET bridge as well as the drive IC and
includes overvoltage shutdown, overtemperature shutdown,
overcurrent shutdown, and undervoltage shutdown.
The device is parametrically specified over ambient temperature
range of -40°C
≤
T
A
≤
125°C and 5.5 V
≤
V
IGN
≤
24 V supply.
Features
• Drives Six N-Channel Low R
DS(ON)
Power MOSFETs
• Built-In Charge Pump Circuitry
• Built-In Current Sense Comparator and Output Drive Current
Limiting
• Built-In PWM Mode Control Logic
• Built-In Circuit Protection
• Designed for Fractional to Integral HP BLDC Motors
• 32-Pin SOIC Wide Body Surface Mount Package
• 33395 Incorporates a <5.0
μs
Shoot-Through Suppression Timer
• 33395T Incorporates a <1.0
μs
Shoot-Through Suppression Timer
• Pb-Free Packaging Designated by Suffix Code EW
33395
33395T
THREE-PHASE
GATE DRIVER IC
ARCHIVE INFORMATION
DWB SUFFIX
EW SUFFIX (Pb-FREE)
98ARH99137A
32-PIN SOICW
ORDERING INFORMATION
Device
MC33395DWB/R2
MC33395EW/R2
MCZ33395EW/R2
MC33395TDWB/R2
MC33395TEW/R2
- 40°C to 125°C
32 SOICW
32 SOICW
(Pb-Free)
Temperature
Range (T
A
)
Package
32 SOICW
32 SOICW
(Pb-Free)
V
PWR
33395
V
DD
VGDH
VIGN
VDD
CP1H
CP1L
CP2H
CP2L
CRES
3
2
3
VIGNP
GDH1
GDH2
GDH3
SRC1
SRC2
SRC3
N
S
N
H
S
H
MCU
HSE1–3
MODE0–1 GDL1
GDL2
PWM
GDL3
LSE1–3
-ISENS
AGND
PGND
+ISENS
V
DD
Figure 1. 33395 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
ARCHIVE INFORMATION
H
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VIGN
VDD
Osc.
Low
Low
Voltage
Reset
Reset
Charge
Charge
Pump
Overvoltage
Overvoltage
Shutdown
CP1H
CP1L
CP2H
CP2L
CPRES
ARCHIVE INFORMATION
+ISENS
-ISENS
+
-
Drive Limiting
Drive Limiting
L
H
VGDH
Control
Control
Logic
Logic
VIGNP
Gate
Drive
Gate
Circuits
Drive
Circuits
GDH1
GDH2
GDH3
SRC1
SRC2
SRC3
GDL1
GDL2
GDL3
MODE0
MODE1
PWM
HSE1
HSE2
HSE3
LSE1
LSE2
LSE3
AGND
TEST
PGND
Overtemperature
Shutdown
Shutdown
Figure 2. 33395 Simplified Internal Block Diagram
33395
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
ARCHIVE INFORMATION
PIN CONNECTIONS
PIN CONNECTIONS
ARCHIVE INFORMATION
16
18
17
Figure 3. 33395 Pin Connections
Table 1. 33395 Pin Definitions
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 9.
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
Pin Name
CP2H
CPRES
VIGN
VGDH
VIGNP
SRC1
GDH1
GDL1
SRC2
GDH2
GDL2
SRC3
GDH3
GDL3
PGND
Test
-ISENS
+ISENS
AGND
VDD
PWM
Input
Input
Output
Input
Sensor
Output
Output
Sensor
Output
Output
Sensor
Output
Output
Ground
N/A
Input
Input
Ground
Power
Input
Pin Function
Formal Name
Charge Pump Cap
Charge Pump
Reserve Cap
Input Voltage
High-Side Gate
Voltage
Input Voltage
Protected
High-Side Sense
Gate Drive High
Output for Gate
High-Side Sense
Gate Drive High
Output for Gate
High-Side Sense
Gate Drive High
Gate Drive Low
Power Ground
Test Pin
IS Minus
IS Plus
Analog Ground
Logic Supply Voltage
Definition
High potential pin connection for secondary charge pump capacitor
Input from external reservoir capacitor for charge pump
Input from ignition level supply voltage for power functions
Output full-time gate drive for auxiliary high-side power MOSFET switch
Input from protected ignition level supply for power functions
Sense for high-side source voltage, phase 1
Output for gate high-side, phase 1
Output for gate drive low-side, phase 1
Sense for high-side source voltage, phase 2
Output for gate high-side, phase 2
Output for gate drive low-side, phase 2
Sense for high-side source voltage, phase 3
Output for gate drive high-side, phase 3
Output for gate drive low-side, phase 3
Ground pins for power functions
This should be connected to ground or left open
Inverting input for current limit comparator
Non-inverting input for current limit comparator
Ground pin for logic functions
Supply voltage for logic functions
Pulse Width Modulator Input for pulse width modulated driver duty cycle
33395
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
ARCHIVE INFORMATION
CP2H
CPRES
VIGN
VGDH
VIGNP
SRC1
GDH1
GDL1
SRC2
GDH2
GDL2
SRC3
GDH3
GDL3
PGND
TEST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
32
31
30
29
28
27
26
25
24
23
22
21
20
19
CP2L
CP1H
CP1L
LSE1
LSE2
LSE3
HSE1
HSE2
HSE3
MODE0
MODE1
PWM
VDD
AGND
+ISENS
-ISENS
PIN CONNECTIONS
Table 1. 33395 Pin Definitions (continued)
A functional description of each pin can be found in the Functional Pin Description section beginning on
page 9.
Pin Number
22
23
24
25
26
27
28
Pin Name
MODE1
MODE0
HSE3
HSE2
HSE1
LSE3
LSE2
LSE1
CP1L
CP1H
CP2L
Pin Function
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Formal Name
Mode Control Bit 1
Mode Control Bit 0
High-Side Enable
High-Side Enable
High-Side Enable
Low-Side Enable
Low-Side Enable
Low-Side Enable
External Pump
Capacitor
External Pump
Capacitor
Charge Pump
Capacitor
Definition
Input for mode control selection
Input for mode control selection
Input for high-side enable logic, phase 3
Input for high-side enable logic, phase 2
Input for high-side enable logic, phase 1
Input for low-side enable logic, phase 3
Input for low-side enable logic, phase 2
Input for low-side enable logic, phase 1
Input from external pump capacitor for charge pump and secondary pins
Input from external pump capacitor for charge pump and secondary pins
Input from external reservoir, external pump capacitors for charge pump,
and secondary pins
ARCHIVE INFORMATION
29
30
31
32
33395
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ARCHIVE INFORMATION
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground unless otherwise noted.
Rating
VIGN Supply Voltage
VIGNP Load Dump Survival
VDD Logic Supply Voltage (Fail Safe)
Symbol
V
IGN
V
IGNP
LD
Value
-15.5 to 40
-0.3 to 65
-0.3 to 7.0
0.3 to 7.0
100
Unit
VDC
VDC
VDC
VDC
mA
V
V
DD
V
IN
I
VIGNSTARTUP
ARCHIVE INFORMATION
Logic Input Voltage (LSEn, HSEn, PWM, and MODEn)
Start Up Current V
IGNP
ESD Voltage
(1)
Human Body Model
Machine Model
Storage Temperature
Operating Ambient Temperature
Operating Case Temperature
Maximum Junction Temperature
Power Dissipation (T
A
= 25°C)
Peak Package Reflow Temperature During Reflow
(2)
,
(3)
Thermal Resistance, Junction-to-Ambient
V
ESD1
V
ESD2
T
STG
T
A
T
C
T
J
P
D
T
PPRT
R
Θ
JA
±500
±200
-65 to 160
-40 to 125
-40 to 125
150
1.5
Note 3
65
°C
°C
°C
°C
W
°C
°C/ W
Notes
1. ESD1 testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
ESD2 testing is performed in
accordance with the Machine Model (C
ZAP
= 200 pF, R
ZAP
= 0
Ω).
2.
3.
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL),
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.
MC33xxxD enter 33xxx), and review parametrics.
33395
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
ARCHIVE INFORMATION
