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MC74AC174, MC74ACT174
Hex D Flip−Flop
with Master Reset
The MC74AC174/74ACT174 is a high−speed hex D flip−flop. The
device is used primarily as a 6−bit edge−triggered storage register. The
information on the D inputs is transferred to storage during the
LOW−to−HIGH clock transition. The device has a Master Reset to
simultaneously clear all flip−flops.
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•
Outputs Source/Sink 24 mA
•
′ACT174
Has TTL Compatible Inputs
V
CC
16
Q
5
15
D
5
14
D
4
13
Q
4
12
D
3
11
Q
3
10
CP
9
16
1
DIP−16
N SUFFIX
CASE 648
16
1
SO−16
D SUFFIX
CASE 751B
1
MR
2
Q
0
3
D
0
4
D
1
5
Q
1
6
D
2
7
Q
2
8
GND
16
Figure 1. Pinout: 16−Lead Packages Conductors
(Top View)
1
TSSOP−16
DT SUFFIX
CASE 948F
PIN ASSIGNMENT
PIN
D
0
−D
5
CP
MR
Q
0
−Q
5
FUNCTION
Data Inputs
Clock Pulse Input
Master Reset Input
Outputs
16
1
EIAJ−16
M SUFFIX
CASE 966
ORDERING INFORMATION
Device
MC74AC174N
MC74ACT174N
MC74AC174D
Package
PDIP−16
PDIP−16
SOIC−16
SOIC−16
SOIC−16
SOIC−16
TSSOP−16
TSSOP−16
EIAJ−16
EIAJ−16
EIAJ−16
EIAJ−16
Shipping
25 Units/Rail
25 Units/Rail
48 Units/Rail
48 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
96 Units/Rail
96 Units/Rail
50 Units/Rail
50 Units/Rail
2000 Tape & Reel
2000 Tape & Reel
TRUTH TABLE
Inputs
MR
L
H
H
H
CP
X
D
X
H
L
X
Output
Q
L
H
L
Q
MC74ACT174D
MC74AC174DR2
MC74ACT174DR2
MC74AC174DT
MC74ACT174DT
MC74AC174DTR2
MC74AC174M
MC74ACT174M
MC74AC174MEL
MC74ACT174MEL
L
TSSOP−16 2500 Tape & Reel
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW−to−HIGH Transition of Clock
DEVICE MARKING INFORMATION
See general marking information in the device marking
section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2006
June, 2006
−
Rev. 7
1
Publication Order Number:
MC74AC174/D
MC74AC174, MC74ACT174
CP
D
0
D
1
D
2
D
3
D
4
D
5
MR
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
The
MC74AC174/74ACT174
consists
of
six
edge−triggered D flip−flops with individual D inputs and Q
outputs. The Clock (CP) and Master Reset (MR) are
common to all flip−flops. Each D input’s state is transferred
to the corresponding flip−flop’s output following the
MR
CP
D
5
D
4
D
3
LOW−to−HIGH Clock (CP) transition. A LOW input to the
Master Reset (MR) will force all outputs LOW independent
of Clock or Data inputs. The MC74AC174/ 74ACT174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
D
2
D
1
D
0
D
CP
CD
Q
D
CP
CD
Q
D
CP
CD
Q
D
CP
CD
Q
D
CP
CD
Q
D
CP
CD
Q
Q
5
NOTE:
Q
4
Q
3
Q
2
Q
1
Q
0
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 3. Logic Diagram
MAXIMUM RATINGS*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
T
stg
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V
CC
or GND Current per Output Pin
Storage Temperature
Value
−0.5
to +7.0
−0.5
to V
CC
+0.5
−0.5
to V
CC
+0.5
±20
±50
±50
−65
to +150
Unit
V
V
V
mA
mA
mA
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
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2
MC74AC174, MC74ACT174
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
t
r
, t
f
Supply Voltage
DC Input Voltage, Output Voltage (Ref. to GND)
Input Rise and Fall Time (Note 1)
′AC
Devices except Schmitt Inputs
Input Rise and Fall Time (Note 2)
′ACT
Devices except Schmitt Inputs
Junction Temperature (PDIP)
Operating Ambient Temperature Range
Output Current
−
High
Output Current
−
Low
V
CC
@ 3.0 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
V
CC
@ 4.5 V
V
CC
@ 5.5 V
Parameter
′AC
′ACT
Min
2.0
4.5
0
−
−
−
−
−
−
−40
−
−
Typ
5.0
5.0
−
150
40
25
10
8.0
−
25
−
−
Max
6.0
5.5
V
CC
−
−
−
−
−
140
85
−24
24
ns/V
°C
°C
mA
mA
ns/V
Unit
V
V
t
r
, t
f
T
J
T
A
I
OH
I
OL
1. V
IN
from 30% to 70% V
CC
; see individual Data Sheets for devices that differ from the typical input rise and fall times.
2. V
IN
from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times.
DC CHARACTERISTICS
74AC
Symbol
Parameter
V
CC
(V)
T
A
= +25°C
Typ
V
IH
Minimum High Level
Input Voltage
Maximum Low Level
Input Voltage
Minimum High Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
V
OL
Maximum Low Level
Output Voltage
3.0
4.5
5.5
3.0
4.5
5.5
I
IN
I
OLD
I
OHD
I
CC
Maximum Input
Leakage Current
†Minimum Dynamic
Output Current
Maximum Quiescent
Supply Current
5.5
5.5
5.5
5.5
1.5
2.25
2.75
1.5
2.25
2.75
2.99
4.49
5.49
−
−
−
0.002
0.001
0.001
−
−
−
−
−
−
−
74AC
T
A
=
−40°C
to
+85°C
Unit
Conditions
Guaranteed Limits
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.56
3.86
4.86
0.1
0.1
0.1
0.36
0.36
0.36
±0.1
−
−
8.0
2.1
3.15
3.85
0.9
1.35
1.65
2.9
4.4
5.4
2.46
3.76
4.76
0.1
0.1
0.1
0.44
0.44
0.44
±1.0
75
−75
80
V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
V
OUT
= 0.1 V
or V
CC
−
0.1 V
I
OUT
=
−50
mA
V
IL
V
V
OH
V
V
*V
IN
= V
IL
or V
IH
−12
mA
I
OH
−24
mA
−24
mA
I
OUT
= 50
mA
V
V
*V
IN
= V
IL
or V
IH
12 mA
I
OL
24 mA
24 mA
V
I
= V
CC
, GND
V
OLD
= 1.65 V Max
V
OHD
= 3.85 V Min
V
IN
= V
CC
or GND
mA
mA
mA
mA
*All outputs loaded; thresholds on input associated with output under test.
†Maximum test duration 2.0 ms, one output loaded at a time.
NOTE: I
IN
and I
CC
@ 3.0 V are guaranteed to be less than or equal to the respective limit @ 5.5 V V
CC
.
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3
MC74AC174, MC74ACT174
AC CHARACTERISTICS
(For Figures and Waveforms
−
See Section 3 of the ON Semiconductor FACT Data Book, DL138/D)
74AC
Symbol
Parameter
V
CC
*
(V)
Min
f
max
t
PLH
t
PHL
t
PHL
Maximum Clock
Frequency
Propagation Delay
CP to Q
n
Propagation Delay
CP to Q
n
Propagation Delay
MR to Q
n
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
90
100
2.0
1.5
2.0
1.5
2.5
1.5
T
A
= +25°C
C
L
= 50 pF
Typ
100
125
9.0
6.0
8.5
6.0
9.0
7.0
Max
−
−
11.5
8.5
11.0
8.0
11.5
9.0
74AC
T
A
=
−40°C
to +85°C
C
L
= 50 pF
Min
70
100
1.5
1.0
1.5
1.0
2.0
1.5
Max
−
−
12.5
9.5
12.0
9.0
12.5
10.5
MHz
ns
ns
ns
3−3
3−6
3−6
3−6
Unit
Fig.
No.
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
AC OPERATING REQUIREMENTS
74AC
Symbol
Parameter
V
CC
*
(V)
Typ
t
s
t
h
t
w
t
w
t
rec
Setup Time, HIGH or LOW
D
n
to CP
Hold Time, HIGH or LOW
D
n
to CP
MR Pulse Width, LOW
CP Pulse Width
Recovery TIme
MR to CP
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
2.5
2.0
1.0
0.5
1.0
1.0
1.0
1.0
0
0
T
A
= +25°C
C
L
= 50 pF
74AC
T
A
=
−40°C
to +85°C
C
L
= 50 pF
Unit
Fig.
No.
Guaranteed Minimum
6.5
5.0
3.0
3.0
5.5
5.0
5.5
5.0
2.5
2.0
7.0
5.5
3.0
3.0
7.0
5.0
7.0
5.0
2.5
2.0
ns
ns
ns
ns
ns
3−9
3−9
3−6
3−6
3−6
*Voltage Range 3.3 V is 3.3 V
±0.3
V.
*Voltage Range 5.0 V is 5.0 V
±0.5
V.
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4
