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Freescale Semiconductor
Data Sheet: Advanced Information
An Energy-Efficient Solution from Freescale
Document Number: MCF51JE256
Rev. 4, 08/2012
MCF51JE256/128
The MCF51JE256 series devices are members of the low-cost,
low-power, high-performance ColdFire V1 family of 32-bit
microcontrollers (MCUs).
Not all features are available in all devices or packages; see
Table 1
for a comparison of features by device.
MCF51JE256/128
80-LQFP
12mm x 12mm
81-BGA
10mm x 10mm
100-LQFP
14mm x 14mm
104-BGA
10mm x 10mm
32-Bit ColdFire V1 Central Processor Unit (CPU)
• Up to 50.33 MHz ColdFire CPU above 2.4 V and 40 MHz CPU above 2.1 V
and 20 MHz CPU above 1.8 V across temperature range of -40°C to
105°C.
• ColdFire Instruction Set Revision C (ISA_C).
• 32-bit multiply and accumulate (MAC) supports signed or unsigned integer
or signed fractional inputs.
On-Chip Memory
• 256 K Flash comprised of two independent 128 K flash arrays;
read/program/erase over full operating voltage and temperature; allows
interrupt processing while programming.
• 32 KB System Random-access memory (RAM).
• Security circuitry to prevent unauthorized access to RAM and Flash
contents.
Power-Saving Modes
• Two ultra-low power stop modes. Peripheral clock enable register can
disable clocks to unused modules to reduce currents.
• Time of Day (TOD) — Ultra low-power 1/4 sec counter with up to 64 sec
timeout.
• Ultra-low power external oscillator that can be used in stop modes to
provide accurate clock source to the TOD. 6 µs typical wake up time from
stop3 mode.
Clock Source Options
• Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz crystal or
ceramic resonator dedicated for TOD operation.
• Oscillator (XOSC2) for high frequency crystal input for MCG reference to
be used for system clock and USB operations.
• Multipurpose Clock Generator (MCG) — PLL and FLL; precision trimming
of internal reference allows 0.2% resolution and typical +0.5% to -1%
deviation over temperature and voltage; supports CPU frequencies up to
50 MHz.
System Protection
• Watchdog computer operating properly (COP) reset with option to run from
dedicated 1 kHz internal clock source or bus clock.
• Low-voltage detection with reset or interrupt; selectable trip points;
separate low voltage warning with optional interrupt; selectable trip points.
• Illegal opcode and illegal address detection with reset.
• Flash block protection for each array to prevent accidental write/erasure.
• Hardware CRC to support fast cyclic redundancy checks.
Development Support
• Integrated ColdFire DEBUG_Rev_B+ interface with single wire BDM
connection supports same electrical interface used by the S08 family
debug modules.
• Real-time debug with 6 hardware breakpoints (4 PC, 1 address and 1
data).
• On-chip trace buffer provides programmable start/stop recording
conditions.
Peripherals
•
USB
— Dual-role USB On-The-Go (OTG) device, supports USB in either
device, host or OTG configuration. On-chip transceiver and 3.3V regulator
help save system cost, fully compliant with USB Specification 2.0. Allows
control, bulk, interrupt and isochronous transfers.
•
SCIx
— Two serial communications interfaces with optional 13-bit break;
option to connect Rx input to PRACMP output on SCI1 and SCI2; High
current drive on Tx on SCI1 and SCI2; wake-up from stop3 on Rx edge.
•
SPI1
— Serial peripheral interface with 32-bit FIFO buffer; 16-bit or 8-bit
data transfers; full-duplex or single-wire bidirectional; double-buffered
transmit and receive; master or slave mode; MSB-first or LSB-first shifting.
•
SPI2
— Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or Slave
mode; MSB-first or LSB-first shifting.
•
IIC
— Up to 100 kbps with maximum bus loading; Multi-master operation;
Programmable slave address; Interrupt driven byte-by-byte data transfer;
supports broadcast mode and 10-bit addressing.
•
CMT
— Carrier Modulator timer for remote control communications.
Carrier generator, modulator and driver for dedicated infrared out (IRO).
Can be used as an output compare timer.
•
TPMx
— Two 4-channel Timer/PWM Module; Selectable input capture,
output compare, or buffered edge- or center-aligned PWM on each
channel; external clock input/pulse accumulator.
•
Mini-FlexBus
— Multi-function external bus interface with user
programmable chip selects and the option to multiplex address and data
lines.
•
PRACMP
— Analog comparator with selectable interrupt; compare option
to programmable internal reference voltage; operation in stop3.
•
ADC12
— 12-bit Successive approximation ADC with up to12
single-ended channels; internal bandgap reference channel; operation in
stop3; fully functional from 3.6V to 1.8V.
•
PDB
— Programmable delay block with 16-bit counter and modulus and
prescale to set reference clock to bus divided by 1 to bus divided by 2048;
8 trigger outputs for ADC module provides periodic coordination of ADC
sampling sequence with sequence completion interrupt; Back-to-Back
mode and Timed mode.
•
DAC
— 12-bit resolution DAC; configurable settling time.
Input/Output
• Up to 68 GPIOs and 1 output-only pin.
• Voltage Reference output (VREFO).
• Dedicated infrared output pin (IRO)
withhigh current sink capability.
• Up to 16 KBI pins with selectable
polarity.
• Up to 16 pins of rapid general purpose
I/O (RGPIO).
This document contains information on a product under development. Freescale reserves the
right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2009-2012. All rights reserved.
Contents
Table of Contents
1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Pinouts and Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.1 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2.2 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.3 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
2.4 80-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.5 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
Preliminary Electrical Characteristics . . . . . . . . . . . . . . . . . .15
3.1 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .15
3.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .15
3.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .16
3.4 ESD Protection Characteristics. . . . . . . . . . . . . . . . . . .18
3.5 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.6 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .21
3.7 PRACMP Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.8 12-bit DAC Electricals . . . . . . . . . . . . . . . . . . . . . . . . . .24
3.9 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .26
3.10 MCG and External Oscillator (XOSC) Characteristics .29
3.11 Mini-FlexBus Timing Specifications . . . . . . . . . . . . . . .32
3.12 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . .34
3.12.2 TPM Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
3.13 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.14 Flash Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.15 USB Electricals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
3.16 VREF Electrical Specifications . . . . . . . . . . . . . . . . . . .41
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.1 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . .44
4.3 Mechanical Drawings . . . . . . . . . . . . . . . . . . . . . . . . . .44
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Figure 13.Timer External Clock . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14.Timer Input Capture Pulse . . . . . . . . . . . . . . . . . . . . .
Figure 15.SPI Master Timing (CPHA = 0) . . . . . . . . . . . . . . . . .
Figure 16.SPI Master Timing (CPHA = 1) . . . . . . . . . . . . . . . . .
Figure 17.SPI Slave Timing (CPHA = 0) . . . . . . . . . . . . . . . . . .
Figure 18.SPI Slave Timing (CPHA = 1) . . . . . . . . . . . . . . . . . .
Figure 19.Typical VREF Output vs Temperature . . . . . . . . . . . .
Figure 20.Typical VREF Output vs V
DD
. . . . . . . . . . . . . . . . . . .
36
36
38
38
39
39
42
43
3
List of Tables
Table 1. MCF51JE Features by MCU and Package. . . . . . . . . . 4
Table 2. MCF51JE256/128 Functional Units. . . . . . . . . . . . . . . . 5
Table 2-3.Package Pin Assignments . . . . . . . . . . . . . . . . . . . . . 11
Table 4. Parameter Classifications . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . 16
Table 6. Thermal Characteristics. . . . . . . . . . . . . . . . . . . . . . . . 17
Table 7. ESD and Latch-up Test Conditions . . . . . . . . . . . . . . . 18
Table 8. ESD and Latch-Up Protection Characteristics. . . . . . . 18
Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10.Supply Current Characteristics . . . . . . . . . . . . . . . . . . 21
Table 11.Stop Mode Adders. . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 12.PRACMP Electrical Specifications . . . . . . . . . . . . . . . 24
Table 13.DAC 12LV Operating Requirements . . . . . . . . . . . . . . 24
Table 14.DAC 12-Bit Operating Behaviors . . . . . . . . . . . . . . . . . 25
Table 15.12-bit ADC Operating Conditions . . . . . . . . . . . . . . . . 26
Table 16.12-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, VREFL = VSSAD) . . . . . . . . . . . . 28
Table 17.MCG (Temperature Range = –40 to 105×C Ambient) . 29
Table 18.XOSC (Temperature Range = –40 to 105×C Ambient) 31
Table 19.Mini-FlexBus AC Timing Specifications . . . . . . . . . . . . 32
Table 20.Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 21.TPM Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 22.SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 23.Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 24.Internal USB 3.3 V Voltage Regulator Characteristics 40
Table 25.VREF Electrical Specifications . . . . . . . . . . . . . . . . . . 41
Table 26.VREF Limited Range Operating Behaviors . . . . . . . . . 42
Table 27.Orderable Part Number Summary. . . . . . . . . . . . . . . . 44
Table 28.Package Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 29.Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
4
5
List of Figures
Figure 1. MCF51JE256/128 Block Diagram. . . . . . . . . . . . . . . . . 3
Figure 2. 104-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 3. 100-Pin LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 4. 81-Pin MAPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 5. 80-Pin LQFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 6. Stop IDD versus Temperature. . . . . . . . . . . . . . . . . . . 23
Figure 7. Offset at Half Scale vs Temperature . . . . . . . . . . . . . . 26
Figure 8. ADC Input Impedance Equivalency Diagram . . . . . . . 28
Figure 9. Mini-FlexBus Read Timing . . . . . . . . . . . . . . . . . . . . . 33
Figure 10.Mini-FlexBus Write Timing . . . . . . . . . . . . . . . . . . . . 33
Figure 11.Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 12.IRQ/KBIPx Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
MCF51JE256 Datasheet, Rev. 4
2
Freescale Semiconductor
VDDA/VSSA
VREFH/VREFL
COCOx
HWTRS[H:A]
PDB
HWTRS[H:A]
Dtrig
ACMPO
PRACMP
PTA7
PTA6
PTA5
PTA4
PTA3/KBI1P2/FB_D6/ADP5
PTA2/KBI1P1/RX1/ADP4
PTA1/KBI1P0/TX1/FB_D1
PTA0/FB_D2/SS1
PTB7/KBI1P4/RGPIOP1/FB_AD0
PTB6/KBI1P3/RGPIOP0/FB_AD17
PTB5/XTAL2
PTB4/EXTAL2
PTB3/XTAL1
PTB2/EXTAL1
PTB1/BLMS
PTB0
PTC7/KBI2P2CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2/FB_D0/FB_AD1
PTC0/MOSI2/FB_OE_b/FB_CS0
PTD7/USB_PULLUP(D+)/RX1
PTD6/USB_ALTCLK/TX1
PTD5/SCL/RGPIOP11/TPM1CH3
PTD4/SDA/RGPIOP10/TPM1CH2
PTD3/USB_PULLUP(D+)/RGPIOP9/TPM1CH1
PTD2/USB_ALTCLK/RGPIOP8/TPM1CH0
PTE7/USB_VBUSVLD/TPM2CH3
PTE6/FB_RW_b/USB_SESSEND/RX2
PTE5/FB_D7/USB_SESSVLD/TX2
PTE3/KBI2P6/FB_AD8
PTE2/KBI2P5/RGPIOP14/FB_AD7
PTE1/KBI2P4/RGPIOP13/FB_AD6
PTE0/KBI2P3/FB_ALE/FB_CS1
PTF7/MISO1
PTF6/MOSI1
PTF5/KBI2P7/FB_D3/FB_AD9
PTF4/SDA/FB_D4/FB_AD10
PTF3/SCL/FB_D5/FB_AD11
PTF2/TX2/USB_DM_DOWN/TPM2CH0
PTF1/RX2/USB_DP_DOWN/TPM2CH1
PTF0/USB_ID/TPM2CH2
PTG7/FB_AD18
PTG6/FB_AD19
PTG5/FB_RW_b
PTG4/USB_SESSVLD
PTG3/USB_DP_DOWN
PTG2/USB_DM_DOWN
PTG1/USB_SESSEND
PTG0/SPSCK1
PTH7/RGPIOP7/FB_D2
PTH6/RGPIOP6/FB_D3
PTH5/RGPIOP5/FB_D4
PTH4/RGPIOP4/FB_D5
PTH3/RGPIOP3/FB_D6
PTH2/RGPIOP2/FB_D7
PTH1/FB_D0
PTH0/FB_OE_b
PTJ7/FB_AD13
PTJ6/FB_AD14
PTJ5/FB_AD15
PTJ4/RGPIOP15/FB_AD16
PTJ3/RGPIOP12/FB_AD5
PTJ2/FB_AD4
PTJ1/FB_AD3
PTJ0/FB_AD2
DADP[3:0]
DADM[3:0]
ADC12
VDDA/VSSA
ADP[11:4]
DADP/M[3:0]
Dtrig
DACO
VREFH/VREFL
DACO
ACMPO
VDDA/VSSA
VREFH/VREFL
SCI1
RX1
TX1
Port B
Port J
Port H
Port G
CLKO
EXTAL1
XTAL1
CLKO
Port F
Port E
Port D
Port C
SCI2
RX2
TX2
VREFO
VREF
IIC
SDA
SCL
KBI1 & KBI2
IRO
CMT
Hardware CRC
DBG
INTC
RGPIO
RGPIO[15:8]
RGPIO[7:0]
REF CLK
IRO:
KBI1P[7:0]
KBI2P[7:0]
4 Ch TPM1
TPM1CH[3:0]
TPMCLK
4 Ch TPM2
TPM2CH[3:0]
TPMCLK
BDM
PTD0/BKGD/MS
BKGD/MS
MCG
IRCLK
SPI1
MOSI1 SS1
MISO1 SPSCK1
Clock Check
& Select
PTD1/CMPP2/RESET
PTE4/CMPP3/
TPMCLK/VPP/IRQ
FB_AD[19:0]
COP
SIM
SPI2
MOSI2 SS2
MISO2 SPSCK2
XOSC2
LVD
FLASH1
128/64 KB
IRQ
MINIFLEX
BUS
Robust
Update
FB_D[7:0]
FB_AD[19:0]
XOSC1
USBOTG
FLASH2
128/64 KB
Manager
RAM
32KB
VREG
USB_DM
USB_DP
USB_ALTCLK
USB_PULLUP(D+)
USB_DM_DOWN
USB_DP_DOWN
USB_VBUSVLD
USB_ID
USB_SESSVLD
USB_SESSEND
TOD
VSS1,2,3
VDD1,2,3
USB_DM
USB_DP
VUSB33
VBUS
Green
pins not available on the 100, 81 or 80 pin package
Blue
pins not available on the 81 or 80 pin package
Red
pin not available on the 80 pin package
Figure 1. MCF51JE256/128 Block Diagram
MCF51JE256 Datasheet, Rev. 4
Freescale Semiconductor
3
control
control
V1 ColdFire Core
with MAC
Port A
Features
1
Features
Table 1. MCF51JE Features by MCU and Package
Feature
FLASH size (bytes)
RAM size (bytes)
Pin quantity
Programmable Analog Comparator (PRACMP)
Debug Module (DBG)
Multipurpose Clock Generator (MCG)
Inter-Integrated Communication (IIC)
Interrupt Request Pin (IRQ)
Keyboard Interrupt (KBI)
Digital General purpose I/O
1
Power and Ground Pins
Time Of Day (TOD)
Serial Communications (SCI1)
Serial Communications (SCI2)
Serial Peripheral Interface (SPI1(FIFO))
Serial Peripheral Interface(SPI2)
Carrier Modulator Timer pin (IRO)
Programmable Delay Block (PDB)
TPM input clock pin (TPMCLK)
TPM1 channels
TPM2 channels
XOSC1
XOSC2
USBOTG
MiniFlex Bus
Rapid GPIO
ADC single-ended channels
DAC ouput pin (DACO)
Voltage reference output pin (VREFO)
1
The following table provides a cross-comparison of the features of the MCF51JE256/128 according to
package.
MCF51JE256
262144
32K
104
100
81
yes
yes
yes
yes
yes
16
69
65
48
8
yes
yes
yes
yes
yes
yes
yes
yes
4
4
yes
yes
yes
yes
16
12
yes
yes
DATA
9
47
48
47
80
81
MCF51JE128
131072
32K
80
Port I/O count does not include BLMS, BKGD and IRQ. BLMS BKGD are Output only, IRQ is input only.
The following table describes the functional units of the MCF51JE256/128.
MCF51JE256 Datasheet, Rev. 4
4
Freescale Semiconductor
