- Up to 240 Individually-Vectored Interrupt Sources
Supported
- 8 Levels of Priority, Individually Assignable By Vector
- Chip-Level Interrupt Aggregator supported, to
expand number of interrupt sources or reduce
number of vectors
- Single byte read/write access
- 32 Byte page size
- 1,000,000 write cycle endurance
• LPC Interface
- Supports LPC Bus frequencies of 19MHz to
33MHz
- 1.8V and 3.3V Support
- LPC I/O Cycles Decoded
- LPC Memory Cycles Decoded
- Clock Run Support
- Serial IRQ
- ACPI SCI interface
- SMI# output
• Enhanced Serial Peripheral Interface (eSPI)
- Intel eSPI Specification compliant
- Supports four channels/interfaces:
-
-
-
-
Peripheral channel Interface
Virtual Wire Interface
Out of Band Channel Interface
Flash Channel Interface
- System Tick Timer
- Complete ARM-Standard Debug Support
- JTAG-Based DAP Port, Comprised of SWJ-DP and
AHB-AP Debugger Access Functions
- Full DWT Hardware Functionality: 4 Data
Watchpoints and Execution Monitoring
- Full FPB Hardware Breakpoint Functionality: 6
Execution Breakpoints and 2 Literal (Data)
Breakpoints
- Supports EC Bus Master to Host Memory
• Legacy Support
- Fast GATEA20 and Fast CPU_RESET
• System to EC Message Interface
- 8042 Style Host Interface
- ACPI Embedded Controller Interface
- Five Instances
- 1 or 4 Byte Data transfer capable
- Full-duplex Register Access
- ACPI Power Management Interface
- SCI Event-Generating Functions
- Comprehensive ARM-Standard Trace Sup-
port
- Full DWT Hardware Trace Functionality for
Watchpoint and Performance Monitoring
- Full ITM Hardware Trace Functionality for
Instrumented Firmware Support and Profiling
- Full ETM Hardware Trace Functionality for
Instruction Trace
- Full TPIU Functionality for Trace Output
Communication
- Mailbox Registers Interface
- Thirty-two 8-Bit Scratch Registers
- Two Register Mailbox Command Interface
- Two Register SMI Source Interface
- Three Embedded Memory Interface
Instances
- Host Serial or Parallel IRQ Source
- Provides Two Windows to On-Chip SRAM for Host
Access
- Two Register Mailbox Command Interface
- Host Access of Virtual Registers Without EC
Intervention
- MPU Feature
- 1µS Delay Register
• Internal Memory
- 64k Boot ROM
- Two blocks of SRAM, totaling 256KB, 320KB
or 480KB
- Each block can be used for either program or data
- One block 32KB or 64KB
- One block 224KB, 288KB or 416KB
• Battery Backed Resources
- Power-Fail Status Register
- 32 KHz Clock Generator
- Week Alarm Timer Interface
- Real Time Clock
- VBAT-Powered Control Interface
- Five Wake-up Input Signals
- Optional Latching of Wake-up Inputs
- 128 Bytes Battery Powered SRAM
- Non-volatile Read/Write Memory
- 2KB of EEPROM
- VBAT-Backed 128 Byte Memory
2016-2018 Microchip Technology Inc.
DS00002206D-page 1
MEC170x
• Four EC-based SMBus 2.0 Host Controllers
- Allows Master or Dual Slave Operation
- Fully Operational on Standby Power
- DMA-driven I
2
C Network Layer Hardware
- I
2
C Datalink Compatibility Mode
- Multi-Master Capable
- Supports Clock Stretching
- Programmable Bus Speed up to 1MHz
- Hardware Bus Access “Fairness” Interface
- SMBus Time-outs Interface
- AMD-TSI Port
- 12 Ports Assignable to Any Controller
- All ports 1.8V-capable
• Five independent Hardware Driven PS/2 Ports
- Three controllers
- Fully functional on Main and/or Suspend Power
- PS/2 Edge Wake Capable
- Two ports 5V tolerant
• Two General Purpose Serial Peripheral Interface
Controllers (ECGP-SPI)
- One 3-pin EC-driven Full Duplex Serial Com-
munication Interface
- One Full Duplex Serial Communication Inter-
face Accessible by Host over LPC
- Flexible Clock Rates
- SPI Burst Capable
• One Quad Serial Peripheral Interface (SPI) Control-
ler
- Master Only SPI Controller
- Mappable to two ports (only 1 port active at a
time)
- Dual and Quad I/O Support
- Flexible Clock Rates
- SPI Burst Capable
- SPI Controller Operates with Internal DMA
Controller with CRC Generation
• 18 x 8 Interrupt Capable Multiplexed Keyboard Scan
Matrix
- Optional Push-Pull Drive for Fast Signal Switch-
ing
• Four Breathing/Blinking LED Interfaces
- Supports three modes of operation:
- Blinking Mode with Programmable Blink Rates
- Breathing LED Output
- 8-bit PWM
- Replacement for Multiple GPIO’s
- Provides 8 Quantized States on One Pin
• General Purpose I/O Pins
- Up to 148 GPIOs
- 8 GPIO Pass-Through Port (GPTP)
- Glitch protection on most GPIO pins
- 6 Battery-powered General Purpose Outputs
- All GPIOs can be powered by 1.8V
- Programmable Drive Strength and Slew Rate
on all GPIOs
• Programmable 16-bit Counter/Timer Interface
- Four 16-bit Auto-reloading Counter/Timer
Instances
- Four Operating Modes per Instance: Timer,
One-shot, Event and Measurement
- 4 External Inputs, 4 External Outputs
• Hibernation Timer Interface
- Two 32.768 KHz Driven 16-bit Timers
- Programmable Wake-up from 0.5ms to 128 Minutes
- One 32.768 KHz Driven 32-bit RTOS Timer
- Programmable Wake-up from 30μS to 35 Hours
- Auto Reload Option
- Breathing LED Supports Piecewise-linear
Brightness Curves, Symmetric or Asymmetric
- Supports Low Power Operation in Blinking and
Breathing Modes
- Operates on Standby Power
- Operates in Chip's Heavy Sleep State on 32kHz
standby clock
- Operational in EC Sleep State
• System Watch Dog Timer (WDT)
• Input Capture and Compare Timer
- 32-bit Free-running timer
- Six 32-bit Capture Registers
- Two 32-bit Compare Registers
- Capture, Compare and Overflow Interrupts
- Toggle Output on Compare Timers
• Week Timer
- Power-up Event Output
- Week Alarm Interrupt with 1 Second to 8.5 Year
Time-out
- Sub-Week Alarm Interrupt with 0.50 Seconds -
72.67 hours time-out
- 1 Second and Sub-second Interrupts
• Real Time Clock (RTC)
- VBAT Powered
- 32KHz Crystal Oscillator
- Time-of-Day and Calendar Registers
- Programmable Alarms
- Supports Leap Year and Daylight Savings Time
• Two Microchip BC-Link Interconnection Bus
- Programmable Bus Clock Rate
• PECI Interface 3.0
• FAN Support
- Eleven Programmable Pulse-Width Modulator
(PWM) Outputs
- Multiple Clock Rates
- 16-Bit ‘On’ and 16-Bit ‘Off’ Counters
- Three Fan Tachometer Inputs
- Two RPM-Based Fan Speed Controllers
-
-
-
-
-
-
-
Each includes one Tach input and one PWM output
3% accurate from 500 RPM to 16k RPM
Automatic Tachometer feedback
Aging Fan or Invalid Drive Detection
Spin Up Routine
Ramp Rate Control
RPM-based Fan Speed Control Algorithm
- Pin buffers capable of sinking up to 12 mA
• Three Resistor/Capacitor Identification Detection
(RC_ID) ports
- Single Pin Interface to External Inexpensive RC
Circuit
DS00002206D-page 2
2016-2018 Microchip Technology Inc.
MEC170x
• ADC Interface
- 10-bit Conversion in 1s
- 16 Channels
- Integral Non-Linearity of ±1.5 LSB; Differential
Non-Linearity of ±1.0 LSB
• Two Standard 16C550 UARTs
- Accessible from Host and EC
- One UART with full 8-pin Modem Control
- One UART with 4-pin Interface
- Programmable Input/output Pin Polarity Inver-
sion
- Programmable Main Power or Standby Power
Functionality
• Two Port 80h Debug Ports for BIOS Debug
- Ports, Assignable to Any LPC IO Address
- 24-bit Timestamp with Adjustable Timebase
- 16-Entry FIFO
• Trace FIFO Debug Port (TFDP)
• Integrated Standby Power Reset Generator
- Reset Input Pin
- Reset Output Pin
• Clock Generator
- 32.768KHz Clock Source
- Low power 32KHz crystal oscillator
- Optional use of a crystal-free silicon oscillator with ±2%
Accuracy
- Optional use of 32.768 KHz input Clock
- Operational on Suspend Power
• Multi-purpose AES Cryptographic Engine
- Hardware support for ECB, CTR, CBC and
OFB AES modes
- Support for 128-bit, 192-bit and 256-bit key
length
- DMA interface to SRAM, shared with Hash
engine
• Cryptographic Hash Engine
- Support for SHA-1, SHA-256, SHA-384, SHA-
512
- DMA interface to SRAM, shared with AES
engine
• Public Key Cryptographic Engine
- Hardware support for RSA and Elliptic Curve
public key algorithms
- RSA keys length of 1024 or 2048 bis
- ECC Prime Field and Binary Field keys up to
640 bits
- Microcoded support for standard public key
algorithms
• Cryptographic Features
- True Random Number Generator
- 1K bit FIFO
- Monotonic Counter
• Packages
- 144 Pin WFBGA RoHS Compliant package
- 169 Pin WFBGA RoHS Compliant package
- Programmable Clock Power Management Con-
trol and Distribution
- 48 MHz PLL
2016-2018 Microchip Technology Inc.
DS00002206D-page 3
MEC170x
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Micro-
chip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined
and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at
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We welcome your feedback.
Most Current Data Sheet
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the
revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
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DS00002206D-page 4
2016-2018 Microchip Technology Inc.
MEC170x
Table of Contents
1.0 General Description ........................................................................................................................................................................ 6
4.0 Power, Clocks, and Resets ......................................................................................................................................................... 148
5.0 ARM M4F Based Embedded Controller ...................................................................................................................................... 166
6.0 RAM and ROM ............................................................................................................................................................................ 176
25.0 Real Time Clock ........................................................................................................................................................................ 394
30.0 Analog to Digital Converter ....................................................................................................................................................... 433
37.0 General Purpose Serial Peripheral Interface ............................................................................................................................ 502
41.0 Trace FIFO Debug Port (TFDP) ................................................................................................................................................ 552
42.0 Port 80 BIOS Debug Port .......................................................................................................................................................... 556
43.0 VBAT-Powered Control Interface .............................................................................................................................................. 562
47.0 Security Features ...................................................................................................................................................................... 589
48.0 Test Mechanisms ...................................................................................................................................................................... 593
