OKI Semiconductor
ML7074-004GA
VoIP CODEC
FEDL7074-004DIGEST-01
Issue Date: Nov. 12, 2003
This document contains minimum specifications. For full specifications, please contact your nearest Oki office or
representative.
GENERAL DESCRIPTION
The ML7074-004GA is a speech CODEC for VoIP. This LSI allows selection of G.729.A, or G.711 standard as a
speech CODEC. The LSI is optimum for adding VoIP functions to TAs, routers, etc., since it has the functions of
an echo canceller for 32 ms delay, DTMF detection, tone detection, tone generation, etc.
FEATURES
•
Single 3.3 V power supply operation (DV
DD
0, 1, 2, AV
DD
: 3.0 to 3.6 V)
•
Speech CODEC:
Selectable among G.729.A (8 kbps), G.711 (64 kbps)
µ-law,
and A-law
Supports PLC (Packet Loss Concealment) function conforming to ITU-T G.711 Appendix I
•
Echo canceller for 32 ms delay
•
DTMF detect function
•
Tone detect function: 2 systems (1650 Hz, 2100 Hz: Detect frequency can be changed.)
•
Tone generate function: 2 systems
•
FSK generation function
•
Dial pulse detect function
•
Dial pulse transmit function
•
Internal 1-channel 16-bit timer
•
Built-in FIFO buffers (640 bytes) for transferring transmit and receive data
Frame/DMA (slave) interface selectable.
•
Master clock frequency: 4.096 MHz (crystal oscillation or external input)
•
Hardware or software power down operation possible.
•
Analog input/output type:
Two built-in input amplifiers
Two built-in output amplifiers, 10 kΩ driving
•
Package:
64-pin plastic QFP (QFP64-P-1414-0.80-BK)
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TONE_DET0
TONE0_DET
TONE1_DET
DTMF_DET
DTMF_CODE[3:0]
OKI Semiconductor
TONE_DET1
DTMF_REC
Speech Codec
Echo Canceller
Encoder
G.729.A
TXGAIN
Sin
LPAD
Sout
BLOCK DIAGRAM
GSX0
Bus Control Unit
10kΩ
AIN0N
TX
Buffer0
TX
Buffer1
Linear PCM
Codec
AIN0P
+
-
ATTs
Center
Clip
GPAD
AMP0
A/D
BPF
GSX1
G.711
TONE_GEN0
(TONEA/B)
10kΩ
AIN1N
STGAIN
AMP1
AFF
TONE_GEN1
(TONEC/D)
Decoder
G.729.A
RXGAIN
10kΩ
VFRO0
G.711
FSK_GEN
FGEN_FLAG
D/A
LPF
Rout
ATTr
Rin
RX
Buffer0
RX
Buffer1
8b
A0-A7
16b
Frame/DMA
Controller
AMP2
10kΩ
VFRO1
AMP3
AVREF
VRE
F
Codec
Decoder
TIMER
DPGEN
DPDET
CR17-B0(GPO0)
CR16-B0(GPI0)
PCMI
S/P
G.711
Control
Register
DP_DET
D0-D15
CSB
RDB
WRB
FR0B
FR1B
ACK0B
ACK1B
PCMO
P/S
Encode
r
PLL
CKGN
MCK
SYNC(8kHz)
G.711
SYNC
OSC
Power
INT
INTB
BCLK
DTMF_DET
DTMF_CODE[3:0]
TONE0_DET
TONE1_DET
DP_DET
FGEN_FLAG
CLKSEL
XI
XO
Serial I/F
PDNB
TST0
TST1
TST2
TST3
DVDD1
DVDD0
DGND0
DGND1
DVDD2
DGND2
AGND
AVDD
GPI0
GPI1
GPO0
GPO1
FEDL7074-003DIGEST-01
ML7074-004GA
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
PIN ASSIGNMENT (TOP VIEW)
DGND1
CLKSEL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DVDD1
GPO1
GPO0
PDNB
GPI1
GPI0
A7
A6
A5
A4
A3
A2
A1
A0
AVDD
49
AIN0P
50
AIN0N
51
GSX0
52
GSX1
53
AIN1N
54
AVREF
55
VFRO0
56
VFRO1
57
AGND
58
DGND2
59
XI
60
XO
61
DVDD2
62
TST3
63
TST2
64
FR0B
10
FR1B
11
INTB
12
CSB
13
RDB
14
WRB
15
DGND0
16
1
2
3
4
5
6
7
8
9
32
31
30
29
28
27
26
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
L7074-004
25
24
23
22
21
20
19
18
17
SYNC
ACK0B
64-pin plastic QFP
DVDD0
ACK1B
PCMO
BCLK
PCMI
TST1
TST0
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
PIN DESCRIPTIONS
Pin
No.
1
2
3
4
5
Symbol
TST1
TST0
PCMO
PCMI
BCLK
I/O PDNB = “0”
I
I
O
I
I/O
“L”
I
6
7
8
9
10
SYNC
DV
DD
0
ACK0B
ACK1B
FR0B
(DMARQ0B)
I/O
“L”
I
I
O
I
I
“H”
“0”
“0”
“Hi-z”
I
I
Description
Test control input 1: Normally input “0”.
Test control input 0: Normally input “0”.
PCM data output
PCM data input
CLKSEL = “0”
PCM shift clock input
CLKSEL = “1”
PCM shift clock output
CLKSEL = “0”
PCM sync signal 8 kHz input
CLKSEL = “1”
PCM sync signal 8 kHz output
Digital power supply
Transmit buffer DMA access acknowledge signal input
Receive buffer DMA access acknowledge signal input
FR0B: (CR11-B7 = “0”)
Transmit buffer frame signal output
DMARQ0B: (CR11-B7 = “1”)
Transmit buffer DMA access request signal output
FR1B: (CR11-B7 = “0”)
Receive buffer frame signal output
DMARQ1B: (CR11-B7 = “1”)
Receive buffer DMA access request signal output
Interrupt request output
“L” level is output for about 1.0
µs
when an interrupt is generated.
Chip select control input
Read control input
Write control input
Digital ground (0.0 V)
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
Data input/output
Fix to input state when using in 8-bit bus access (CR11-B5 = “1”).
11
FR1B
(DMARQ1B)
INTB
CSB
RDB
WRB
DGND0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
O
“H”
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
O
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
“H”
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
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FEDL7074-003DIGEST-01
OKI Semiconductor
ML7074-004GA
Pin
No.
33
34
35
36
37
38
39
40
41
42
Symbol
DV
DD
1
A0
A1
A2
A3
A4
A5
A6
A7
PDNB
I/O PDNB = “0”
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
“0”
Description
Digital power supply
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Address input
Power down input
“0”: Power down reset
“1”: Normal operation
SYNC and BCLK I/O control input
“0”: SYNC and BCLK become inputs
“1”: SYNC and BCLK become outputs
Digital ground (0.0 V)
General-purpose input pin 0 (5 V tolerant input)
/Secondary function: Dial pulse detect input pin
General-purpose input pin 1 (5 V tolerant input)
General-purpose output pin 0 (5 V tolerant output, can be pulled up
externally)
/Secondary function: Dial pulse transmit pin
General-purpose output pin 1 (5 V tolerant output, can be pulled up
externally)
Analog power supply
AMP0 non-inverted input
AMP0 inverted input
AMP0 output (10 kΩ driving)
AMP1 output (10 kΩ driving)
AMP1 inverted input
Analog signal ground (1.4 V)
AMP2 Output (10 kΩ driving)
AMP3 Output (10 kΩ driving)
Analog ground (0.0 V)
Digital ground (0.0 V)
4.096 MHz crystal oscillator I/F, 4.096 MHz clock input
4.096 MHz crystal oscillator I/F
Digital power supply
Test control input 3: Normally input “0”.
Test control input 2: Normally input “0”.
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
CLKSEL
DGND1
GPI0
GPI1
GPO0
GPO1
AV
DD
AIN0P
AIN0N
GSX0
GSX1
AIN1N
AVREF
VFRO0
VFRO1
AGND
DGND2
XI
XO
DV
DD
2
TST3
TST2
I
I
I
O
O
I
I
O
O
I
O
O
O
I
O
I
I
I
I
I
“L”
“L”
I
I
“Hi-z”
“Hi-z”
I
“L”
“Hi-z”
“Hi-z”
I
“H”
“0”
“0”
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