Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
E2L0068-19-61
¡ Semiconductor
¡ Semiconductor
MSM54V25632A
DESCRIPTION
This version: Jun. 1999
MSM54V25632A
Previous version: Sep. 1998
131,072-Word
¥
32-Bit
¥
2-Bank Synchronous Graphics RAM
The MSM54V25632A is a synchronous graphics random access memory organized as 128 K words
¥
32 bits
¥
2 banks.
This device can operate up to 100 MHz by using synchronous interface. In addition, it has 8-column
Block Write function and Write per bit function which improves performance in graphics
systems.
FEATURES
• 131,072 words
¥
32 bits
¥
2 banks memory
• Single 3.3 V
±0.3
V power supply
• LVTTL compatible inputs and outputs
• All input signals are latched at rising edge of system clock
• Auto precharge and controlled precharge
• Internal pipelined operation: column address can be changed every clock cycle
• Dual internal banks controlled by A9 (Bank Address: BA)
• Independent byte operation via DQM0 to DQM3
• 8-column Block Write function
• Persistent write per bit function
• Programmable burst sequence (Sequential/Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable
CAS
latency (1, 2 and 3)
• Burst stop function (full-page burst)
• Power Down operation and Clock Suspend operation
• Auto refresh and self refresh capability
• 1,024 refresh cycles/16 ms
• Package:
100-pin plastic QFP
(QFP100-P-1420-0.65-BK4)
(Product : MSM54V25632A-xxAGBK4)
xx indicates speed rank.
PRODUCT FAMILY
Family
MSM54V25632A-10
MSM54V25632A-12
Clock Frequency
MHz (Max.)
100
83
Package
100-pin Plastic QFP (14
¥
20 mm)
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¡ Semiconductor
PIN CONFIGURATION (TOP VIEW)
100
DQ2
99
V
SS
Q
82
V
SS
Q
81
DQ29
84
DQ31
83
DQ30
98
DQ1
97
DQ0
96
V
CC
95
NC
86
NC
85
V
SS
94
NC
93
NC
92
NC
91
NC
90
NC
89
NC
88
NC
87
NC
DQ3
V
CC
Q
DQ4
DQ5
V
SS
Q
DQ6
DQ7
V
CC
Q
DQ16
DQ17
V
SS
Q
DQ18
DQ19
V
CC
Q
V
CC
V
SS
DQ20
DQ21
V
SS
Q
DQ22
DQ23
V
CC
Q
DQM0
DQM2
WE
CAS
RAS
CS
BA (A9)
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
MSM54V25632A
80
DQ28
79
V
CC
Q
78
DQ27
77
DQ26
76
V
SS
Q
75
DQ25
74
DQ24
73
V
CC
Q
72
DQ15
71
DQ14
70
V
SS
Q
69
DQ13
68
DQ12
67
V
CC
Q
66
V
SS
65
V
CC
64
DQ11
63
DQ10
62
V
SS
Q
61
DQ9
60
DQ8
59
V
CC
Q
58
NC
57
DQM3
56
DQM1
55
CLK
54
CKE
53
DSF
52
NC
51
A8
37
38
39
40
41
42
43
44
45
46
47
48
A0
A1
A2
A3
V
CC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
SS
A4
A5
A6
A7
100-Pin Plastic QFP
Pin Name
A0 - A9
A0 - A8
A0 - A7
A9
DQ0 - DQ31
CS
RAS
CAS
WE
Function
Address Inputs
Row Address Inputs
Column Address Inputs
Bank Address
Data Inputs/Outputs
Chip Select
Row Address Strobe
Column Address Strobe
Write Enable
Pin Name
DQM0 - DQM3
DSF
CKE
CLK
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Function
DQ Mask Enable
Special Function Enable
Clock Enable
System Clock Input
Supply Voltage
Ground
Supply Voltage for DQ
Ground for DQ
No Connection
Note:
The same power supply voltage must be provided to every V
CC
pin and V
CC
Q pin.
The same GND voltage level must be provided to every V
SS
pin and V
SS
Q pin.
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49
50
¡ Semiconductor
MSM54V25632A
BLOCK DIAGRAM
Refresh
Counter
Row Decoders
Timing
Generator
4Mb
Memory Cells
Bank - A
Sense Amplifiers
Column Decoders
Row Decoders
CLK
CKE
CS
RAS
CAS
WE
DSF
V
CC
V
SS
Address Buffers
A0
A1
A2
32
I/O Buffers
DQ0 to 31
A9
4Mb
Memory Cells
Bank - B
Sense Amplifiers
Column Decoders
32
32
DQM0 to 3
Color
Register
(32 bits)
Mask
Register
(32 bits)
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¡ Semiconductor
MSM54V25632A
PIN DESCRIPTION
CLK
CS
CKE
Fetches all inputs at the "H" edge.
Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,
DQM0, DQM1, DQM2 and DQM3.
Masks system clock to deactivate the subsequent CLK operation.
If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is
deactivated. CKE should be asserted at least one cycle prior to a new command.
Address
Row & column multiplexed.
Row address: RA0 – RA8
Column address: CA0 – CA7
BA (A9)
RAS
CAS
WE
DSF
DQM0 -
DQM3
DQi
DSF is part of the inputs of graphics command of the MSM54V25632A.
If DSF is inactive (Low level), MSM54V25632A operates just like SDRAM.
Masks the read data of two clocks later when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Masks the write data of the same clock when DQM0 - DQM3 are set "H" at the "H" edge of the clock signal.
Data inputs/outputs are multiplexed on the same pin.
1. When
CS
is set "High" at a clock transition from "Low" to "High", all inputs except CLK, CKE, DQM0,
DQM1, DQM2, and DQM3 are invalid.
2. When issuing an active, read or write command, the bank is selected by A9.
Functionality depends on the combination. For details, see the function truth table.
Selects bank to be activated during row address latch time and selects bank for precharge and read/
write during column address latch time. A9 = "L" : Bank A, A9 = "H" : Bank B
*
Notes:
A9
0
1
Active, read or write
Bank A
Bank B
3. The auto precharge function is enabled or disabled by the A8 input when the read or write command is
issued.
A8
0
1
0
1
A9
0
0
1
1
Operation
After the end of burst, bank A holds the active status.
After the end of burst, bank A is precharged automatically.
After the end of burst, bank B holds the active status.
After the end of burst, bank B is precharged automatically.
4. When issuing a precharge command, the bank to be precharged is selected by the A8 and A9 inputs.
A8
0
0
1
A9
0
1
X
Operation
Bank A is precharged.
Bank B is precharged.
Both banks A and B are precharged.
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