Dear customers,
About the change in the name such as "Oki Electric Industry Co. Ltd." and
"OKI" in documents to OKI Semiconductor Co., Ltd.
The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI
Semiconductor Co., Ltd. on October 1, 2008.
Therefore, please accept that although
the terms and marks of "Oki Electric Industry Co., Ltd.", “Oki Electric”, and "OKI"
remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.".
It is a change of the company name, the company trademark, and the logo, etc. , and
NOT a content change in documents.
October 1, 2008
OKI Semiconductor Co., Ltd.
550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan
http://www.okisemi.com/en/
OKI Semiconductor
MSM80C85AHRS/GS/JS
8-Bit CMOS MICROPROCESSOR
FEDL80C85AH-03
Issue Date: May
16,
2003
This product is not available in Asia and Oceania.
GENRAL DESCRIPTION
The MSM80C85AH is a complete 8-bit parallel; central processor implemented in silicon gate
C-MOS technology and compatible with MSM80C85A.
It is designed with higher processing speed (max.5 MHz) and lower power consumption
compared with MSM80C85A and power down mode is provided, thereby offering a high level
of system integration.
The MSM80C85AH uses a multiplexed address/data bus. The address is split between the 8-
bit address bus and the 8-bit data bus. The on-chip address latch : of a MSM81C55-5 memory
product allows a direct interface with the MSM80C85AH.
FEATURES
• Power down mode (HALT-HOLD)
• Low Power Dissipation: 50mW(Typ)
• Single + 3 to + 6 V Power Supply
• –40 to + 85°C, Operating Temperature
• Compatible with MSM80C85A
• 0.8
ms
instruction Cycle (V
CC
= 5V)
• On-Chip Clock Generator (with External Crystal)
• On-Chip System Controller; Advanced Cycle Status Information Available for Large System
Control
g p
• Four Vectored interrupt (One is non-maskable) Plus the 8080A-compatible interrupt.
• Serial, In/Serial Out Port
• Decimal, Binary and Double Precision Arithmetic
• Addressing Capability to 64K Bytes of Memory
• TTL Compatible
• 40-pin Plastic DIP(DIP40-P-600-2.54): (MSM80C85AHRS)
• 44-pin Plastic QFJ(QFJ44-P-S650-1.27): (MSM80C85AHJS)
• 44-pin Plastic QFP(QFP44-P-910-0.80-2K): (MSM80C85AHGS-2K)
1
¡ Semiconductor
MSM80C85AHRS/GS/JS
FUNCTIONAL BLOCK DIAGRAM
RST
INTR
INTA
5.5 6.5
7.5 TRAP
SID
SOD
Interrupt Control
Serial I/O Control
8-Bit Internal Data Bus
Accumulator
(8)
Temporary Register
(8)
Flag (5)
Flip Flops
Instruction
Register (8)
Arithmetic
Logic Unit
ALU(8)
Instruction
Decoder
And
Machine
Cycle
Encoding
B REG (8)
D REG (8)
H REG (8)
C REG (8)
E REG (8)
C REG (8)
Register
Array
Stack Pointer (16)
Program Counter (16)
Incrementer/Decrementer
Address Latch (16)
Power
Supply
+5V
GND
Power Down
X
1
X
2
CLK
GEN
Timing And Control
Control
Status
DMA
Reset
Address Buffer (8)
Data/Address
Buffer (8)
CLK
OUT
READY
RD WR
ALE
S0
S1 IO /
M
HOLD HLDA
RESET IN
RESET OUT
A
15
- A
8
Address Bus
AD
7
- AD
0
Address/Data Bus
2
¡ Semiconductor
MSM80C85AHRS/GS/JS
PIN CONFIGURATION (TOP VIEW)
40 pin Plastic DIP
X
1
X
2
RESET OUT
SOD
SID
TRAP
RST7.5
RST6.5
RST5.5
INTR
INTA
AD
0
AD
1
AD
2
AD
3
AD
4
AD
5
AD
6
AD
7
GND
33 READY
32 IO/M
31 S
1
30
RD
29
WR
28 ALE
27 S
0
26 A
15
25 A
14
24 A
13
23 A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
CC
HOLD
HLDA
CLK(OUT)
RESET IN
READY
IO/M
S
1
RD
WR
ALE
S
0
A
15
A
14
A
13
A
12
A
11
A
10
A
9
A
8
44 pin Plastic QFP
42 RESET OUT
35 CLK(OUT)
TRAP 1
RST7.5 2
RST6.5 3
RST5.5 4
INTR 5
INTA
6
AD
0
7
AD
1
8
AD
2
9
AD
3
10
NC 11
34
RESET IN
37 HOLD
36 HLDA
43 SOD
38 V
CC
44 SID
39 NC
41 X
2
40 X
1
44 pin Plastic QFJ
4 RESET OUT
AD
4
12
AD
5
13
AD
6
14
AD
7
15
GND 16
V
CC
17
A
8
18
A
9
19
A
10
20
A
11
21
NC 22
41 CLK(OUT)
TRAP 7
RST7.5 8
RST6.5 9
RST5.5 10
INTR 11
NC 12
INTA
13
AD
0
14
AD
1
15
AD
2
16
AD
3
17
40
RESET IN
39 READY
38 IO/M
37 S
1
36
RD
35
WR
34 NC
33 ALE
32 S
0
31 A
15
30 A
14
29 A
13
43 HOLD
A
9
25
AD
4
18
NC 19
AD
5
20
AD
6
21
AD
7
22
GND 23
A
8
24
A
10
26
42 HLDA
5 SOD
44 V
CC
6 SID
1 NC
3 X
2
2 X
1
A
11
27
A
12
28
3
¡ Semiconductor
MSM80C85AHRS/GS/JS
MSM80C85AH FUNCTIONAL PIN DEFINITION
The following describes the function of each pin:
Symbol
A
8
- A
15
(Output, 3-state)
A
0
- A
7
(Input/Output)
3-state
ALE
(Output)
Function
Address Bus: The most significant 8-bits of the memory address or the 8-bits of the I/O address,
3-stated during Hold and Halt modes and during RESET.
Multiplexed Address/Data Bus: Lower 8-bits of the memory address (or I/O address) appear on
the bus during the first clock cycle (T state) of a machine cycle. It then becomes the data bus during
the second and third clock cycles.
Address Latch Enable: It occurs during the first clock state of a machine cycle and enables address to
get latched into the on-chip latch peripherals. The falling edge of ALE is set to guarantee setup and
hold times for the address information. The falling edge ALE can also be used to strobe the status
information ALE is never 3-state.
Machine cycle status:
IO/M S
1
S
0
0
0
1
1
0
0
1
0
1
1
1
0
1
0
1
States
IO/M S
1
S
0
1
.
.
.
1
0
·
·
1
0
·
·
States
Interrupt Acknowledge
Halt
= 3-state
Hold
(high impedance)
Reset
·
= unspecified
S
0
, S
1
, IO/M
(Output)
Memory write
Memory read
I/O write
I/O read
Opcode fetch
S
1
can be used as an advanced R/W status. IO/M, S
0
and S
1
become valid at the beginning of
a machine cycle and remain stable throughout the cycle. The falling edge of ALE may be used to latch
the state of these lines.
RD
(Output, 3-state)
WR
(Output, 3-state)
READY
(Input)
READ control: A low level on
RD
indicates the selected memory or I/O device is to be read that
the Data Bus is available for the data transfer, 3-stated during Hold and Halt modes and during RESET.
WRITE control: A low level on
WR
indicates the data on the Data Bus is to be written into the selected
memory or I/O location. Data is set up at the trailing edge of
WR,
3-stated during Hold and Halt
modes and during RESET.
If READY is high during a read or write cycle, it indicates that the memory or peripheral is ready to
send or receive data. If READY is low, the cpu will wait an integral number of clock cycles for READY
to go high before completing the read or write cycle READY must conform to specified setup and
hold times.
HOLD indicates that another master is requesting the use of the address and data buses.
The cpu, upon receiving the hold request, will relinquish the use of the bus as soon as the completion
of the current bus transfer. Internal processing can continue. The processor can regain the bus only
after the HOLD is removed. When the HOLD is acknowledged, the Address, Data,
RD, WR,
and IO/M
lines are 3-stated. And status of power down is controlled by HOLD.
HOLD ACKNOWLEDGE: Indicates that the cpu has received the HOLD request and that it will
relinquish the bus in the next clock cycle. HLDA goes low after the Hold request is removed.
The cpu takes the bus one half clock cycle after HLDA goes low.
INTERRUPT REQUEST: Is used as a general purpose interrupt. It is sampled on during the next to
the last clock cycle of an instruction and during Hold and Halt states. If it is active, the Program
Counter (PC) will be inhibited from incrementing and an
INTA
will be issued. During this cycle
a RESTART or CALL instruction can be inserted to jump to the interrupt service routine.
The INTR is enabled and disabled by software. It is disabled by Reset and immediately after
an interrupt is accepted. Power down mode is reset by INTR.
INTERRUPT ACKNOWLEDGE: Is used instead of (and has the same timing as)
RD
during
the instruction cycle after an INTR is accepted.
RESTART INTERRUPTS: These three inputs have the same timing as INTR except they cause
an internal RESTART to be automatically inserted.
The priority of these interrupts is ordered as shown in Table 1. These interrupts have a higher priority
than INTR. In addition, they may be individually masked out using the SIM instruction.
Power down mode is reset by these interrupts.
Trap interrupt is a nonmaskable RESTART interrupt. It is recognized at the same timing as INTR or
RST 5.5 - 7.5. It is unaffected by any mask or Interrupt Disable. It has the highest priority of any
interrupt. (See Table 1.) Power down mode is reset by input of TRAP.
HOLD
(Input)
HLDA
(Output)
INTR
(Output)
INTA
(Output)
RST 5.5
RST 6.5
RST 7.5
(Input)
TRAP
(Input)
4
