ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
SMALL-OUTLINE
DRAM MODULE
FEATURES
• JEDEC pinout in a 72-pin, small-outline, dual in-
line memory module (SODIMM)
• 16MB (4 Meg x 32) and 32MB (8 Meg x 32)
• High-performance CMOS silicon-gate process
• Single +3.3V ±0.3V power supply
• All inputs, outputs and clocks are TTL-compatible
• 4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• Optional self refresh (S) for low-power data retention
MT2LDT432H (X)(S), MT4LDT832H (X)(S)
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT (Front View)
72-Pin Small-Outline DIMM
1
OPTIONS
• Package
72-pin SODIMM (gold)
• Timing
50ns access
60ns access
• Access Cycles
FAST PAGE MODE
EDO PAGE MODE
• Refresh Rates
Standard Refresh
Self Refresh (128ms period)
MARKING
G
-5
-6
None
X
None
S
PIN
FRONT
PIN
1
V
SS
2
3
DQ1
4
5
DQ3
6
7
DQ5
8
9
DQ7
10
11
PRD1
12
13
A1
14
15
A3
16
17
A5
18
19
A10
20
21
DQ8
22
23
DQ10
24
25
DQ12
26
27
DQ14
28
29
A11
30
31
A8
32
33 NC/RAS3#* 34
35
DQ15
36
*32MB version only
BACK
DQ0
DQ2
DQ4
DQ6
V
DD
A0
A2
A4
A6
NC
DQ9
DQ11
DQ13
A7
V
DD
A9
RAS2#
NC
PIN
FRONT
PIN
37
DQ16
38
39
V
SS
40
41
CAS2#
42
43
CAS1#
44
45 NC/RAS1#* 46
47
WE#
48
49
DQ18
50
51
DQ20
52
53
DQ22
54
55
NC
56
57
DQ25
58
59
DQ28
60
61
V
DD
62
63
DQ30
64
65
NC
66
67
PRD3
68
69
PRD5
70
71
PRD7
72
BACK
DQ17
CAS0#
CAS3#
RAS0#
NC (A12)
NC (A13)
DQ19
DQ21
DQ23
DQ24
DQ26
DQ27
DQ29
DQ31
PRD2
PRD4
PRD6
V
SS
PART NUMBERS
EDO Operating Mode
PART NUMBER
MT2LDT432HG-x X
MT2LDT432HG-x XS
MT4LDT832HG-x X
MT4LDT832HG-x XS
x = speed
CONFIGURATION
4 Meg x 32
4 Meg x 32
8 Meg x 32
8 Meg x 32
REFRESH
Standard
Self
Standard
Self
NOTE:
Symbols in parentheses are not used on these modules but may
be used for other modules in this product family. They are for
reference only.
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
FPM Operating Mode
PART NUMBER
MT2LDT432HG-x
MT2LDT432HG-x S
MT4LDT832HG-x
MT4LDT832HG-x S
x = speed
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
84ns
104ns
50ns
60ns
20ns
25ns
25ns
30ns
13ns
15ns
8ns
10ns
CONFIGURATION
4 Meg x 32
4 Meg x 32
8 Meg x 32
8 Meg x 32
REFRESH
Standard
Self
Standard
Self
FPM Operating Mode
SPEED
-5
-6
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
90ns
110ns
50ns
60ns
30ns
35ns
25ns
30ns
13ns
15ns
30ns
40ns
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
GENERAL DESCRIPTION
The MT2LDT432H (X)(S) and MT4LDT832H (X)(S)
are randomly accessed 16MB and 32MB memories
organized in a small-outline x32 configuration. They
are specially processed to operate from 3V to 3.6V for
low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the address bits, which are entered
12 bits (A0-A11) at a time. RAS# is used to latch the first
12 bits and CAS# the latter 10 bits.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. If WE# goes
LOW prior to CAS# going LOW, the output pin(s)
remain open (High-Z) until the next CAS# cycle.
FAST-PAGE-MODE READ, except data will be held
valid or become valid after CAS# goes HIGH, as long as
RAS# and OE# are held LOW. (Refer to the 4 Meg x 16
[MT4LC4M16R6] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every
t
REF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing.
An optional self refresh mode is also available. The
“S” option allows the user the choice of a fully static,
low-power data retention mode or a dynamic refresh
mode at the extended refresh period of 128ms. The
optional self refresh feature is initiated by performing
a CBR REFRESH cycle and holding RAS# LOW for the
specified
t
RASS.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows
for the completion of any internal refresh cycles that
may be in process at the time of the RAS# LOW-to-
HIGH transition. If the DRAM controller uses a distrib-
uted refresh sequence, a burst refresh is not required
upon exiting self refresh. However, if the DRAM con-
troller utilizes a RAS#-ONLY or burst refresh sequence,
all rows must be refreshed within the average internal
refresh rate, prior to the resumption of normal opera-
tion.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-address-
defined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version,
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (
t
CP) to occur without the out-
put data going invalid. This elimination of CAS#
output control provides for pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT2LDT432H (X)(S) (16MB)
12
A0-A11
WE#
U1
DQ0-
DQ15
CAS0#
CAS1#
RAS0#
A0-A11
WE#
CASL#
CASH#
RAS#
OE#
16
12
32
DQ0-DQ31
12
A0-A11
WE#
U2
DQ16-
DQ31
CAS2#
CAS3#
RAS2#
CASL#
CASH#
RAS#
OE#
16
V
DD
V
SS
U1-U2
U1-U2
U1-U2 = MT4LC4M16R6TG (S) EDO PAGE MODE
U1-U2 = MT4LC4M16F5TG (S) FAST PAGE MODE
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT832H (X)(S) (32MB)
12
A0-A11
WE#
U1
DQ0-
DQ15
CAS0#
CAS1#
RAS0#
CASL#
CASH#
RAS#
OE#
16
32
DQ0-DQ31
12
WE#
CAS2#
CAS3#
RAS2#
A0-A11
A0-A11
WE#
U2
DQ16-
DQ31
CASL#
CASH#
RAS#
16
12
OE#
12
A0-A11
WE#
CASL#
CASH#
U3
DQ0-
DQ15
16
RAS1#
RAS#
OE#
32
DQ0-DQ31
12
A0-A11
WE#
U4
DQ16-
DQ31
CASL#
CASH#
RAS3#
RAS#
OE#
16
V
DD
V
SS
U1-U4
U1-U4
U1-U4 = MT4LC4M16R6TG (S) EDO PAGE MODE
U1-U4 = MT4LC4M16F5TG (S) FAST PAGE MODE
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
ADVANCE
4, 8 MEG x 32
DRAM SODIMMs
JEDEC-DEFINED
PRESENCE-DETECT – MT2LDT432H (X)(S) (16MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7
PIN
11
66
67
68
69
70
71
-5
NC
NC
V
SS
NC
V
SS
V
SS
X*
-6
NC
NC
V
SS
NC
NC
NC
X*
JEDEC-DEFINED
PRESENCE-DETECT – MT4LDT832H (X)(S) (32MB)
SYMBOL
PRD1
PRD2
PRD3
PRD4
PRD5
PRD6
PRD7
PIN
11
66
67
68
69
70
71
-5
NC
NC
V
SS
V
SS
V
SS
V
SS
X*
-6
NC
NC
V
SS
V
SS
NC
NC
X*
*X = NC (Normal Refresh) or V
SS
(Self Refresh)
4, 8 Meg x 32 DRAM SODIMMs
DM89.p65 – Rev. 12/98
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1998, Micron Technology, Inc.
