4MB, 8MB (x32)
SDRAM DIMMs
SYNCHRONOUS
DRAM MODULE
Features
• JEDEC pinout in a 100-pin, dual in-line memory
module (DIMM)
• 4MB (1 Meg x32) and 8MB (2 Meg x32)
• Utilizes 100 MHz and 125 MHz SDRAM components
• Single +3.3V power supply
• Fully synchronous; all signals registered on positive
edge of system clock
• Internal SDRAM device pipelined operation,
compatible with 2n prefetch architecture, allows
column address changes every clock cycle
• Internal SDRAM device banks for hiding row
access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge and Auto Refresh Modes
64ms, 2,048-cycle refresh (31.25µs refresh interval for
power saving); or 64ms, 2,048-cycle refresh (15.625µs
refresh interval)
• LVTTL-compatible inputs and outputs
•
Serial Presence-Detect (SPD
)
MT2LSDT132U - 4MB
MT4LSDT232UD - 8MB
For the latest data sheet, please refer to the Micron
â
Web
site:
www.micron.com/moduleds
Figure 1: 100-Pin DIMM (MO–161)
OPTIONS
• Package
100-pin DIMM (Gold)
100-pin DIMM (Lead-free)
• Frequency / CAS Latency
125 MHz (8ns) / CL = 3
100 MHz (10ns) / CL = 2
MARKING
G
Y
-8
-10
Table 2:
Table 1:
Timing Parameters
CL = CAS (READ) latency
MODULE
CLOCK
SETUP HOLD
MARKING FREQUENCY CL = 2 CL = 3 TIME TIME
-8
-10
125 MHz
100 MHz
–
10ns
6ns
–
2ns
2ns
1ns
1ns
ACCESS TIME
Part Numbers
CONFIGURATION
1 Meg x32
1 Meg x32
1 Meg x32
1 Meg x32
2 Meg x32
2 Meg x32
2 Meg x32
2 Meg x32
SYSTEM BUS
SPEED
125 MHz
125 MHz
100 MHz
100 MHz
125 MHz
125 MHz
100 MHz
100 MHz
PART NUMBER
MT2LSDT132UG-8_
MT2LSDT132UY-8_
MT2LSDT132UG-10_
MT2LSDT132UY-10_
MT4LSDT232UDG-8_
MT4LSDT232UDY-8_
MT4LSDT232UDG-10_
MT4LSDT232UDY-10_
Table 3:
Address Table
4MB
2K or 4K
2 (BA0)
MODULE DENSITY
8MB
2K or 4K
2 (BA0)
Refresh Count
Device Banks
Device Configuration
Device Row Addressing
Device Column Addressing
Module Ranks
1 Meg x 16
2K (A0 - A10)
1 Meg x 16
2K (A0 - A10)
256 (A0 - A7)
1 (S0#, S2#)
256 (A0 - A7)
2 (S0#, S2#; S1#, S3#)
09005aef80948ad4
SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
4MB, 8MB (x32)
SDRAM DIMMs
Table 4:
Pin Assignment Front
(100-Pin DIMM)
SYMBOL
A0
A2
A4
A6
A8
A10
NC
NC
V
DD
NC
RFU
RFU
CK0
PIN
26
27
28
29
30
31
32
33
34
35
36
37
SYMBOL PIN SYMBOL
Vss
CKE0
WE#
S0#
S2#
V
DD
NC
NC
NC
NC
Vss
DQMB2
38
39
40
41
42
43
44
45
46
47
48
49
50
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
DQ21
DQ22
DQ23
Vss
SDA
SCL
V
DD
Table 5:
Pin Assignment Back
(100-Pin DIMM)
SYMBOL
A1
A3
A5
A7
A9
BA0
NC
NC
V
DD
RAS#
CAS#
RFU
CK1
PIN
76
77
78
79
80
81
82
83
84
85
86
87
SYMBOL
Vss
CKE1
NC
S1#
S3#
V
DD
NC
NC
NC
NC
Vss
DQMB3
PIN SYMBOL
88
89
90
91
92
93
94
95
96
97
98
99
100
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
Vss
SA0
SA1
SA2
PIN SYMBOL PIN
1
Vss
13
2
DQ0
14
3
DQ1
15
4
DQ2
16
5
DQ3
17
6
V
DD
18
7
DQ4
19
8
DQ5
20
9
DQ6
21
10
DQ7
22
11 DQMB0 23
12
Vss
24
25
PIN SYMBOL PIN
51
Vss
63
52
DQ8
64
53
DQ9
65
54 DQ10
66
55 DQ11
67
56
V
DD
68
57 DQ12
69
58 DQ13
70
59 DQ14
71
60 DQ15
72
61 DQMB1 73
62
Vss
74
75
Figure 2: Pin Locations (100-Pin DIMM)
Front View
U1
U2
U5
PIN 1
PIN 23
PIN 50
Back View
(Not populated for the 4MB module)
U4
U3
PIN100
PIN 73
PIN 51
Indicates a V
DD
pin
Indicates a V
SS
pin
09005aef80948ad4
SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
4MB, 8MB (x32)
SDRAM DIMMs
Table 6:
PIN NUMBER
28, 72, 73
25, 75
Pin Descriptions
SYMBOL
WE#, RAS#,
CAS#
CK0, CK1
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS# and WE# (along with S#) define the command
being entered.
Clock: CK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge SDRAM input signals are sampled on the positive edge
of CK. CK also increments the internal burst counter and controls the output
registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH operation
(all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE
is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CK, are disabled during power-down and self
refresh modes, providing low standby power.
Chip Select: S# enables (registered LOW) or disables (registered HIGH) the
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQMB is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-
Z state (after a two-clock latency) when DQMB is sampled HIGH during a
READ cycle.
Bank Address: BA0 defines to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank.
A10 is sampled during a PRECHARGE command to determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank selected by
BA0) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE REGISTER command.
Serial Clock for Presence-Detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to configure the
presence-detect device.
Data I/Os: Data bus.
Pin numbers may not correlate with symbols. Refer to the Pin Assignment Tables on page 2 for more information.
27, 77
CKE0, CKE1
Input
29, 30, 79, 80
S0#-S3#
Input
11, 37, 61, 87
DQMB0-
DQMB3
Input
68
13, 14, 15, 16, 17,
18, 63, 64, 65, 66,
67
BA0
A0-A10
Input
Input
49
98-100
2-5, 7-10, 38-41,
43-46, 52-55, 57-
60, 88-91, 93-96
48
SCL
SA0-SA2
DQ0-DQ31
Input
Input
Input/
Output
SDA
6, 21, 31, 42, 50,
56, 71, 81, 92
1, 12, 26, 36, 47,
51, 62, 76, 86, 97
23, 24, 74
19, 20, 22, 32-35,
69, 70, 78, 82-85
V
DD
V
SS
RFU
NC
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
Output addresses and data into and data out of the presence-detect portion of the
module.
Supply Power Supply: +3.3V ±0.3V.
Supply Ground.
–
–
Reserved for Future Use: These pins should be left unconnected.
Not connected.
09005aef80948ad4
SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
4MB, 8MB (x32)
SDRAM DIMMs
Figure 3: Functional Block Diagram ( MT2LSDT132U)
S0#
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQML CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
S2#
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RAS#
CAS#
CKE0
WE#
A0-A10
BA0
V
DD
V
SS
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs
WE#: SDRAMs
A0-A10: SDRAMs
BA0: SDRAMs
SDRAMs
SCL
SDRAMs
WP
A0
CK1
10pF
SPD
DQML CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK0
6.8pF
U1
U2
U5
A1
A2
SA0 SA1 SA2
SDA
NOTE:
1. All resistor values are 22
W
unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as refer-
enced in the Module Part Numbering Guide at
www.micron.com/numberguide.
SDRAMs = MT48LC1M16A1TG
09005aef80948ad4
SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.
4MB, 8MB (x32)
SDRAM DIMMs
Figure 4: Functional Block Diagram (MT4LSDT232UD)
S1#
S0#
DQMB0
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB1
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
S3#
S2#
DQMB2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
RAS#
CAS#
CKE0
CKE1
WE#
A0-A10
BA0
V
DD
V
SS
DQML CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U2
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs U1-U2
CKE: SDRAMs U3-U4
WE#: SDRAMs
A0-A10: SDRAMs
BA0: SDRAMs
SPD
SDRAMs
SDRAMs
SA0 SA1 SA2
SCL
WP
A0
CK1
6.8pF
U3
U4
DQML CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U4
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
CK0
6.8pF
U1
U2
DQML CS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U1
DQ
DQMH
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQML CS#
U3
DQMH
U5
A1
A2
SDA
NOTE:
1. All resistor values are 22
W
unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as
referenced in the Module Part Numbering Guide at
www.micron.com/
numberguide.
SDRAMs = MT48LC1M16A1TG
09005aef80948ad4
SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology Inc.