MT4LSDT232UDY-10XX,MT4LSDT232UDY-10XX pdf中文资料,MT4LSDT232UDY-10XX引脚图,MT4LSDT232UDY-10XX电路-Datasheet-电子工程世界

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4MB, 8MB (x32)

SDRAM DIMMs

SYNCHRONOUS

DRAM MODULE

Features

• JEDEC pinout in a 100-pin, dual in-line memory

module (DIMM)

• 4MB (1 Meg x32) and 8MB (2 Meg x32)

• Utilizes 100 MHz and 125 MHz SDRAM components

• Single +3.3V power supply

• Fully synchronous; all signals registered on positive

edge of system clock

• Internal SDRAM device pipelined operation,

compatible with 2n prefetch architecture, allows

column address changes every clock cycle

• Internal SDRAM device banks for hiding row

access/precharge

• Programmable burst lengths: 1, 2, 4, 8, or full page

• Auto Precharge and Auto Refresh Modes

64ms, 2,048-cycle refresh (31.25µs refresh interval for

power saving); or 64ms, 2,048-cycle refresh (15.625µs

refresh interval)

• LVTTL-compatible inputs and outputs

•

Serial Presence-Detect (SPD

)

MT2LSDT132U - 4MB

MT4LSDT232UD - 8MB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Figure 1: 100-Pin DIMM (MO–161)

OPTIONS

• Package

100-pin DIMM (Gold)

100-pin DIMM (Lead-free)

• Frequency / CAS Latency

125 MHz (8ns) / CL = 3

100 MHz (10ns) / CL = 2

MARKING

-8

-10

Table 2:

Table 1:

Timing Parameters

CL = CAS (READ) latency

MODULE

CLOCK

SETUP HOLD

MARKING FREQUENCY CL = 2 CL = 3 TIME TIME

-8

-10

125 MHz

100 MHz

–

10ns

6ns

–

2ns

1ns

ACCESS TIME

Part Numbers

CONFIGURATION

1 Meg x32

2 Meg x32

SYSTEM BUS

SPEED

125 MHz

100 MHz

125 MHz

100 MHz

PART NUMBER

MT2LSDT132UG-8_

MT2LSDT132UY-8_

MT2LSDT132UG-10_

MT2LSDT132UY-10_

MT4LSDT232UDG-8_

MT4LSDT232UDY-8_

MT4LSDT232UDG-10_

MT4LSDT232UDY-10_

Table 3:

Address Table

4MB

2K or 4K

2 (BA0)

MODULE DENSITY

8MB

2K or 4K

2 (BA0)

Refresh Count

Device Banks

Device Configuration

Device Row Addressing

Device Column Addressing

Module Ranks

1 Meg x 16

2K (A0 - A10)

1 Meg x 16

2K (A0 - A10)

256 (A0 - A7)

1 (S0#, S2#)

256 (A0 - A7)

2 (S0#, S2#; S1#, S3#)

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4MB, 8MB (x32)

SDRAM DIMMs

Table 4:

Pin Assignment Front

(100-Pin DIMM)

SYMBOL

A10

RFU

CK0

SYMBOL PIN SYMBOL

Vss

CKE0

WE#

S0#

S2#

Vss

DQMB2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

Vss

SDA

SCL

Table 5:

Pin Assignment Back

(100-Pin DIMM)

SYMBOL

BA0

RAS#

CAS#

RFU

CK1

SYMBOL

Vss

CKE1

S1#

S3#

Vss

DQMB3

PIN SYMBOL

100

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

Vss

SA0

SA1

SA2

PIN SYMBOL PIN

Vss

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

11 DQMB0 23

Vss

PIN SYMBOL PIN

Vss

DQ8

DQ9

54 DQ10

55 DQ11

57 DQ12

58 DQ13

59 DQ14

60 DQ15

61 DQMB1 73

Vss

Figure 2: Pin Locations (100-Pin DIMM)

Front View

PIN 1

PIN 23

PIN 50

Back View

(Not populated for the 4MB module)

PIN100

PIN 73

PIN 51

Indicates a V

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4MB, 8MB (x32)

SDRAM DIMMs

Table 6:

PIN NUMBER

28, 72, 73

25, 75

Pin Descriptions

SYMBOL

WE#, RAS#,

CAS#

CK0, CK1

TYPE

Input

DESCRIPTION

Command Inputs: RAS#, CAS# and WE# (along with S#) define the command

being entered.

Clock: CK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge SDRAM input signals are sampled on the positive edge

of CK. CK also increments the internal burst counter and controls the output

registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.

Deactivating the clock provides POWER-DOWN and SELF REFRESH operation

(all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE

is synchronous except after the device enters power-down and self refresh

modes, where CKE becomes asynchronous until after exiting the same mode.

The input buffers, including CK, are disabled during power-down and self

refresh modes, providing low standby power.

Chip Select: S# enables (registered LOW) or disables (registered HIGH) the

the command decoder. All commands are masked when S# is registered

HIGH. S# is considered part of the command code.

Input/Output Mask: DQMB is an input mask signal for write accesses and an

output enable signal for read accesses. Input data is masked when DQMB is

sampled HIGH during a WRITE cycle. The output buffers are placed in a High-

Z state (after a two-clock latency) when DQMB is sampled HIGH during a

READ cycle.

Bank Address: BA0 defines to which bank the ACTIVE, READ, WRITE or

PRECHARGE command is being applied.

Address Inputs: Provide the row address for ACTIVE commands, and the

column address and auto precharge bit (A10) for READ/WRITE commands, to

select one location out of the memory array in the respective device bank.

A10 is sampled during a PRECHARGE command to determines whether the

PRECHARGE applies to one device bank (A10 LOW, device bank selected by

BA0) or all device banks (A10 HIGH). The address inputs also provide the op-

code during a LOAD MODE REGISTER command.

Serial Clock for Presence-Detect: SCL is used to synchronize the presence-

detect data transfer to and from the module.

Presence-Detect Address Inputs: These pins are used to configure the

presence-detect device.

Data I/Os: Data bus.

Pin numbers may not correlate with symbols. Refer to the Pin Assignment Tables on page 2 for more information.

27, 77

CKE0, CKE1

Input

29, 30, 79, 80

S0#-S3#

Input

11, 37, 61, 87

DQMB0-

DQMB3

Input

13, 14, 15, 16, 17,

18, 63, 64, 65, 66,

BA0

A0-A10

Input

98-100

2-5, 7-10, 38-41,

43-46, 52-55, 57-

60, 88-91, 93-96

SCL

SA0-SA2

DQ0-DQ31

Input

Input/

Output

SDA

6, 21, 31, 42, 50,

56, 71, 81, 92

1, 12, 26, 36, 47,

51, 62, 76, 86, 97

23, 24, 74

19, 20, 22, 32-35,

69, 70, 78, 82-85

RFU

Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer

Output addresses and data into and data out of the presence-detect portion of the

module.

Supply Power Supply: +3.3V ±0.3V.

Supply Ground.

–

Reserved for Future Use: These pins should be left unconnected.

Not connected.

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4MB, 8MB (x32)

SDRAM DIMMs

Figure 3: Functional Block Diagram ( MT2LSDT132U)

S0#

DQMB0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

DQML CS#

DQMH

S2#

DQMB2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

RAS#

CAS#

CKE0

WE#

A0-A10

BA0

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs

WE#: SDRAMs

A0-A10: SDRAMs

BA0: SDRAMs

SDRAMs

SCL

SDRAMs

CK1

10pF

SPD

DQML CS#

DQMH

CK0

6.8pF

SA0 SA1 SA2

SDA

NOTE:

1. All resistor values are 22

unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as refer-

enced in the Module Part Numbering Guide at

www.micron.com/numberguide.

SDRAMs = MT48LC1M16A1TG

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4MB, 8MB (x32)

SDRAM DIMMs

Figure 4: Functional Block Diagram (MT4LSDT232UD)

S1#

S0#

DQMB0

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQMB1

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

S3#

S2#

DQMB2

DQ16

DQ17

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

DQMB3

DQ24

DQ25

DQ26

DQ27

DQ28

DQ29

DQ30

DQ31

RAS#

CAS#

CKE0

CKE1

WE#

A0-A10

BA0

DQML CS#

DQMH

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs U1-U2

CKE: SDRAMs U3-U4

WE#: SDRAMs

A0-A10: SDRAMs

BA0: SDRAMs

SPD

SDRAMs

SA0 SA1 SA2

SCL

CK1

6.8pF

DQML CS#

DQMH

CK0

6.8pF

DQML CS#

DQMH

DQML CS#

DQMH

SDA

NOTE:

1. All resistor values are 22

unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as

referenced in the Module Part Numbering Guide at

www.micron.com/

numberguide.

SDRAMs = MT48LC1M16A1TG

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

参数对比

与MT4LSDT232UDY-10XX相近的元器件有：MT2LSDT132UG-8XX、MT4LSDT232UDG-10XX、MT2LSDT132UY-10XX、MT4LSDT232UDY-8XX、MT4LSDT232UDG-8XX、MT2LSDT132UY-8XX、MT2LSDT132UG-10XX。描述及对比如下：

型号	MT4LSDT232UDY-10XX	MT2LSDT132UG-8XX	MT4LSDT232UDG-10XX	MT2LSDT132UY-10XX	MT4LSDT232UDY-8XX	MT4LSDT232UDG-8XX	MT2LSDT132UY-8XX	MT2LSDT132UG-10XX
描述	Synchronous DRAM Module, 2MX32, 7.5ns, CMOS, DIMM-100	Synchronous DRAM Module, 1MX32, 6ns, CMOS, DIMM-100	Synchronous DRAM Module, 2MX32, 7.5ns, CMOS, DIMM-100	Synchronous DRAM Module, 1MX32, 7.5ns, CMOS, DIMM-100	Synchronous DRAM Module, 2MX32, 6ns, CMOS, DIMM-100	Synchronous DRAM Module, 2MX32, 6ns, CMOS, DIMM-100	Synchronous DRAM Module, 1MX32, 6ns, CMOS, DIMM-100	Synchronous DRAM Module, 1MX32, 7.5ns, CMOS, DIMM-100
零件包装代码	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM	DIMM
针数	100	100	100	100	100	100	100	100
Reach Compliance Code	compliant	compliant	unknown	compliant	compliant	unknown	compliant	compliant
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	DUAL BANK PAGE BURST	DUAL BANK PAGE BURST	SINGLE BANK PAGE BURST	SINGLE BANK PAGE BURST
最长访问时间	7.5 ns	6 ns	7.5 ns	7.5 ns	6 ns	6 ns	6 ns	7.5 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 代码	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100	R-XDMA-N100
内存密度	67108864 bit	33554432 bit	67108864 bit	33554432 bit	67108864 bit	67108864 bit	33554432 bit	33554432 bit
内存集成电路类型	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE	SYNCHRONOUS DRAM MODULE
内存宽度	32	32	32	32	32	32	32	32
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	100	100	100	100	100	100	100	100
字数	2097152 words	1048576 words	2097152 words	1048576 words	2097152 words	2097152 words	1048576 words	1048576 words
字数代码	2000000	1000000	2000000	1000000	2000000	2000000	1000000	1000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C	70 °C
组织	2MX32	1MX32	2MX32	1MX32	2MX32	2MX32	1MX32	1MX32
封装主体材料	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED	UNSPECIFIED
封装形状	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY	MICROELECTRONIC ASSEMBLY
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
最大供电电压 (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V	3.6 V
最小供电电压 (Vsup)	3 V	3 V	3 V	3 V	3 V	3 V	3 V	3 V
标称供电电压 (Vsup)	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V	3.3 V
表面贴装	NO	NO	NO	NO	NO	NO	NO	NO
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
端子形式	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD	NO LEAD
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL
是否无铅	不含铅	含铅	-	不含铅	不含铅	-	不含铅	含铅
是否Rohs认证	符合	不符合	-	符合	符合	-	符合	不符合
厂商名称	Micron Technology	-	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology	Micron Technology
峰值回流温度（摄氏度）	260	235	-	260	260	-	260	235
处于峰值回流温度下的最长时间	30	30	-	30	30	-	30	30