OP-07 Low Offset Low Drift Operational Amplifier
December 1994
OP-07 Low Offset Low Drift Operational Amplifier
General Description
The OP-07 has very low input offset voltage which is ob-
tained by trimming at the wafer stage These low offset volt-
ages generally eliminate any need for external nulling The
OP-07 also features low input bias current and high open-
loop gain The low offsets and high open-loop gain make
the OP-07 particularly useful for high-gain applications
The wide input voltage range of
g
13V minimum combined
with high CMRR of 110 dB and high input impedance pro-
vide high accuracy in the non-inverting circuit configuration
Excellent linearity and gain accuracy can be maintained
even at high closed-loop gains
Stability of offsets and gain with time or variation in temper-
ature is excellent
The OP-07 is available in TO-99 metal can ceramic or
molded DIP
For improved specifications see the LM607
Features
Y
Y
Y
Y
Y
Y
Y
Y
Low V
OS
75
mV
Max
Low V
OS
Drift
0 6
mV
C Max
Ultra-Stable vs Time
1 0
mV
Month Max
Low Noise
0 6
mVp-p
Max
g
14V
Wide Input Voltage Range
g
3V to
g
18V
Wide Supply Voltage Range
Fits 725 108A 308A 741 AD510 Sockets
Replaces the
mA714
Applications
Y
Y
Y
Y
Strain Gauge Amplifiers
Thermocouple Amplifiers
Precision Reference Buffer
Analog Computing Functions
Connection Diagram
Dual-In-Line Package
TL H 10550 – 1
See NS Package Number N08E
Ordering Information
T
A
e
25 C
V
OS
Max
(mV)
75
150
150
Also available per SMD
N08E
Plastic
OP07EP
OP07CP
OP07DP
8203602
Operating
Temperature
Range
COM
COM
COM
C
1995 National Semiconductor Corporation
TL H 10550
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
g
22V
Supply Voltage
Internal Power Dissipation (Note 5)
Differential Input Voltage
Input Voltage (Note 6)
Output Short-Circuit Duration
500 mW
g
30V
g
22V
Storage Temperature Range
Lead Temperature (Soldering 60 sec )
Junction Temperature
b
65 C to
a
150 C
260 C
b
65 C to
a
150 C
Operating Temperature Range
OP-07E OP-07C OP-07D
0 C to
a
70 C
Continuous
Simplified Schematic
TL H 10550 – 3
R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage
2
Electrical Characteristics
Unless otherwise specified V
S
e
g
15V T
A
e
25 C
Boldface
type refers to limits over 0 C
s
T
A
s
70 C
Symbol
V
OS
V
OS t
I
OS
I
B
e
np-p
e
n
Parameter
Input Offset Voltage
Long-Term V
OS
Stability
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage
Density
Input Noise Current
Input Noise Current
Density
Input Resistance
Differential-Mode
Input Resistance
Common-Mode
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large Signal
Voltage Gain
V
CM
e
g
13V
V
S
e
g
3V to
g
18V
V
S
e
g
3V to
g
18V
R
L
t
2 kX V
O
e
g
10V
R
L
t
2 kX
R
L
t
500X V
O
e
g
0 5V
V
S
e
g
3V (Note 4)
R
L
t
10 kX
R
L
t
2 kX
R
L
t
2 kX
R
L
t
1 kX
R
L
t
2 kX (Note 3)
A
VCL
e a
1 (Note 3)
V
O
e
0 I
O
e
0
V
S
e
g
15V No Load
V
S
e
g
3V No Load
R
P
e
20 kX
(Note 4)
200
180
150
g
12 5
g
12 0
g
12 0
g
10 5
g
13 0
Conditions
Min
(Note 1)
(Note 2)
OP-07E
Typ
30
45
03
05
09
g
1 2
g
1 5
OP-07C
Max
75
130
15
38
53
g
4 0
g
5 5
Units
Max
150
250
20
60
80
g
7 0
g
9 0
Min
Typ
60
85
04
08
16
g
1 8
g
2 2
mV
mV
Mo
nA
nA
mV
p-p
nV
0
Hz
pA
p-p
pA
0
Hz
0 1 Hz to 10 Hz (Note 3)
f
O
e
10 Hz
f
O
e
100 Hz (Note 3)
f
O
e
1000 Hz
0 1 Hz to 10 Hz (Note 3)
f
O
e
10 Hz
f
O
e
100 Hz (Note 3)
f
O
e
1000 Hz
(Note 4)
15
0 35
10 3
10 0
96
14
0 32
0 14
0 12
50
160
g
14 0
06
18 0
13 0
11 0
30
0 80
0 23
0 17
8
0 38
10 5
10 2
98
15
0 35
0 15
0 13
33
120
g
13
g
14
0 65
20 0
13 5
11 5
35
0 90
0 27
0 18
i
np-p
i
n
R
IN
R
INCM
IVR
CMRR
PSRR
A
VO
MX
GX
V
dB
32
51
mV
V
106
103
123
123
5
7
500
450
400
g
13 0
g
12 8
g
12 6
g
12 0
100
97
20
32
120
100
100
g
12 0
g
11 5
g
11 0
120
120
7
10
400
400
400
g
13 0
g
12 8
g
12 6
g
12 0
V mV
V
O
Output Voltage Swing
V
SR
BW
R
O
P
d
Slew Rate
Closed-Loop Bandwidth
Output Resistance
Power Consumption
Offset Adj Range
01
04
03
06
60
75
4
g
4
01
04
03
06
60
V
ms
MHz
X
150
8
mW
mV
18
mV
C
120
6
80
4
g
4
TCV
OS
TCV
OS
n
TCI
OS
TCI
B
Average Input Offset
Voltage Drift Without
External Trim
With External Trim
Average Input Offset
Current Drift
Average Input Bias
Current Drift
03
13
05
R
P
e
20 kX (Note 4)
(Note 3)
(Note 3)
03
8
13
3
13
35
35
04
12
18
16
50
50
pA C
pA C
Electrical Characteristics
Unless otherwise specified V
S
e
g
15V T
A
e
25 C
Boldface
type refers to limits over 0 C
s
T
A
s
a
70 C
Symbol
V
OS
V
OS t
I
OS
I
B
e
np-p
e
n
Parameter
Input Offset Voltage
Long-Term V
OS
Stability
Input Offset Current
Input Bias Current
Input Noise Voltage
Input Noise Voltage Density
0 1 Hz to 10 Hz (Note 3)
f
O
e
10 Hz
f
O
e
100 Hz (Note 3)
f
O
e
1000 Hz
0 1 Hz to 10 Hz (Note 3)
f
O
e
10 Hz
f
O
e
100 Hz (Note 3)
f
O
e
1000 Hz
(Note 4)
7
Conditions
Min
(Note 1)
(Note 2)
OP-07D
Typ
60
85
05
08
16
g
2 0
g
3 0
Units
Max
150
250
30
60
80
g
12 0
g
14 0
mV
mV
Mo
nA
nA
mVp-p
nV
0
Hz
pAp-p
pA
0
Hz
0 38
10 5
10 3
98
15
0 35
0 15
0 13
31
120
g
13
g
14
0 65
20 0
13 5
11 5
35
0 90
0 27
0 18
i
np-p
i
n
Input Noise Current
Input Noise Current Density
R
IN
R
INCM
IVR
CMRR
PSRR
A
VO
Input Resistance Differential-Mode
Input Resistance Common-Mode
Input Voltage Range
Common-Mode
Rejection Ratio
Power Supply
Rejection Ratio
Large Signal
Voltage Gain
MX
GX
V
dB
32
51
mV
V
V
CM
e
g
13V
V
S
e
g
3V to
g
18V
R
L
s
2 kX V
O
e
g
10V
R
L
e
2 kX V
O
e
g
10V
R
L
t
500X V
O
e
g
0 5V
V
S
g
3V (Note 4)
R
L
t
10 kX
R
L
t
2 kX
R
L
t
2 kX
R
L
t
1 kX
R
L
t
2 kX (Note 3)
A
VCL
e a
1 (Note 3)
V
O
e
0 I
O
e
0
V
S
e
g
15V No Load
V
S
e
g
3V No Load
R
P
e
20 kX
(Note 4)
94
94
110
106
7
10
120
100
400
400
400
V mV
V
O
Output Voltage Swing
g
12 0
g
11 5
g
11 0
g
13 0
g
12 8
g
12 6
g
12 0
V
SR
BW
RO
P
d
Slew Rate
Closed-Loop Bandwidth
Output Resistance
Power Consumption
Offset Adj Range
01
04
03
06
60
80
4
g
4
V
ms
MHz
X
150
8
mW
mV
25
mV
C
TCV
OS
TCV
OS
n
TCI
OS
TCI
B
Average Input Offset
Voltage Drift Without
External Trim
With External Trim
Average Input Offset Current Drift
Average Input Bias Current Drift
07
R
P
e
20 kX (Note 4)
(Note 3)
(Note 3)
07
12
18
25
50
50
mV
C
pA C
pA C
Note 1
V
OS
is measured approximately 0 5 second after application of power
Note 2
Long-Term Offset Voltage Stability refers to the averaged trend line of V
OS
vs Time over extended periods after the first 30 days of operation
Excluding the initial hour of operation changes in V
OS
during the first 30 operating days are typically 2 5
mV
Parameter is sample tested
Note 3
Sample Tested
Note 4
Guaranteed by design
4
Test Circuits
Offset Voltage Test Circuit
Low Frequency Noise Test Circuit
TL H 10550 – 4
TL H 10550 – 5
Optional Offset Nulling Circuit
TL H 10550 –6
5
