Si53102-A1/A2/A3 Data Sheet
PCI-Express Gen 1, Gen 2, Gen 3, and Gen 4 1:2 Fan-out Clock
Buffer
Si53102-A1/A2/A3 is a family of high-performance 1:2 PCIe fan output buffers. This low-
additive-jitter clock buffer family is compliant to PCIe Gen 1, Gen 2, Gen 3, and Gen 4
specifications. The ultra-small footprint (1.4x1.6 mm) and industry-leading low power
consumption make the Si53102-A1/A2/A3 the ideal clock solution for consumer and em-
bedded applications. Measuring PCIe clock jitter is quick and easy with the Silicon Labs
PCIe Clock Jitter Tool. Download it for free at
www.silabs.com/pcie-learningcenter.
Applications
• Network Attached Storage
• Multi-function Printer
• Wireless Access Point
• Server/Storage
KEY FEATURES
• PCI-Express Gen 1, Gen 2, Gen 3, and
Gen 4 common clock compliant
• Two low-power PCIe clock outputs
• Supports Serial-ATA (SATA) at 100 MHz
• No termination resistors required for
differential clocks
• 2.5 V or 3.3 V Power supply
• Spread Spectrum Tolerant
• Extended Temperature Range
• –40 to 85 °C
• Small package 8-pin TDFN (1.4 x 1.6 mm)
• For PCIe Gen 1: Si53102-A1
• For PCIe Gen 2: Si53102-A2
• For PCIe Gen 3/4: Si53102-A3
VDD
DIFFIN
DIFFIN
DIFF1
DIFF2
VSS
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Rev. 1.4
Si53102-A1/A2/A3 Data Sheet
Ordering Guide
1. Ordering Guide
Table 1.1. Ordering Guide
Part Number
Si53102-A1-GM
Si53102-A1-GMR
Si53102-A2-GM
Si53102-A2-GMR
Si53102-A3-GM
Si53102-A3-GMR
Package Type
8-pin TDFN
8-pin TDFN—Tape and Reel
8-pin TDFN
8-pin TDFN—Tape and Reel
8-pin TDFN
8-pin TDFN—Tape and Reel
Temperature
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
Extended, –40 to 85 °C
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Rev. 1.4 | 2
Table of Contents
1. Ordering Guide
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3. Test and Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . 7
4. Recommended Design Guideline . . . . . . . . . . . . . . . . . . . . . . . . 9
5. Pin Descriptions
6. Package Outline
7. Land Pattern
8. Revision History
8.1 Revision 1.0
8.2 Revision 1.1
8.3 Revision 1.2
8.4 Revision 1.3
8.5 Revision 1.4
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Rev. 1.4 | 3
Si53102-A1/A2/A3 Data Sheet
Electrical Specifications
2. Electrical Specifications
Table 2.1. Recommended Operating Conditions
Parameter
Supply Voltage (3.3 V Sup-
ply)
Supply Voltage (2.5 V Sup-
ply)
Symbol
V
DD
V
DD
Test Condition
3.3 V ± 10%
2.5 V ± 10%
Min
2.97
2.25
Typ
3.3
2.5
Max
3.63
2.75
Unit
V
V
Table 2.2. DC Electrical Specifications
Parameter
Operating Voltage (V
DD
=
3.3 V)
Operating Voltage (V
DD
=
2.5 V)
Operating Supply Current
Input Pin Capacitance
Output Pin Capacitance
Symbol
V
DD
V
DD
I
DD
C
IN
C
OUT
Test Condition
3.3 V ± 10%
2.5 V ± 10%
Full Active
Input Pin Capacitance
Output Pin Capacitance
Min
2.97
2.25
—
—
—
Typ
3.30
2.5
—
3
—
Max
3.63
2.75
15
5
5
Unit
V
V
mA
pF
pF
Table 2.3. AC Electrical Specifications
1, 2, 3
Parameter
DIFFIN at 0.7 V
Input frequency
DIFFIN and DIFFINb
Rising/Falling Slew Rate
Differential Input High Volt-
age
Differential Input Low Volt-
age
Crossing Point Voltage at
0.7 V Swing
Vcross Variation Over All
edges
Differential Ringback Volt-
age
Time before Ringback Al-
lowed
Absolute Maximum Input
Voltage
Absolute Minimum Input
Voltage
V
IH
V
IL
V
OX
ΔV
OX
V
RB
T
STABLE
V
MAX
V
MIN
–0.3
Single-ended measurement
Single-ended measurement
Fin
T
R
/ T
F
Single ended measurement:
V
OL
= 0.175 to V
OH
= 0.525
V (Averaged)
150
—
250
—
–100
500
—
—
—
—
—
—
—
—
—
–150
550
140
100
—
1.15
—
mV
mV
mV
mV
mV
ps
V
V
10
0.6
100
—
175
4
MHz
V/ns
Symbol
Condition
Min
Typ
Max
Unit
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Rev. 1.4 | 4
Si53102-A1/A2/A3 Data Sheet
Electrical Specifications
Parameter
DIFFIN and DIFFINb Duty
Cycle
Rise/Fall Matching
Symbol
T
DC
T
RFM
Condition
Measured at crossing point
VOX
Determined as a fraction of
2 x (TR – TF)/(TR + TF)
DIFF Clocks
Duty Cycle
Output Skew
Frequency Accuracy
Slew Rate
T
DC
T
SKEW
F
ACC
t
r/f2
Measured at crossing point
VOX
Measured at 0 V differential
All output clocks
Measured differentially from
±150 mV
PCIe Gen 1 Pk-Pk Additive
Jitter
PCIe Gen 2 Additive Phase
Jitter
PCIe Gen 2 Additive Phase
Jitter
PCIe Gen 3 Additive Phase
Jitter
Pk-Pk
GEN1
PCIe Gen 1
Si53102-A1
RMS
GEN2
10 kHz < F < 1.5 MHz,
Si53102-A2
RMS
GEN2
1.5 MHz < F < Nyquist,
Si53102-A2
RMS
GEN3
Includes PLL BW 2–4 MHz,
CDR = 10 MHz,
Si53102-A3, VDD=3.3 V
Includes PLL BW 2–4 MHz,
CDR = 10 MHz,
Si53102-A3, VDD=2.5V
PCIe Gen 4 Additive Phase
Jitter
Crossing Point Voltage at
0.7 V Swing
Enable/Disable and Setup
Clock Stabilization from
Powerup
T
STABLE
Power up to first output
—
—
3.0
ms
RMS
GEN4
PCIe Gen4, VDD=3.3V
PCIe Gen4, VDD=2.5V
V
OX
VDD = 3.3 V
VDD = 2.5 V
300
200
—
—
—
—
0.22
0.25
550
550
ps
ps
mV
mV
—
—
0.25
ps
—
—
0.22
ps
—
—
0.50
ps
—
—
0.50
ps
—
—
10
ps
45
—
—
0.6
—
—
—
—
55
100
100
4.0
%
ps
ppm
V/ns
Min
45
—
Typ
—
—
Max
55
20
Unit
%
%
Note:
1. Visit
www.pcisig.com
for complete PCIe specifications
2. Gen 4 specifications based on the PCI-Express Base Specification 4.0 rev. 0.5.
3. Download the Silicon Labs PCIe Clock Jitter Tool at
www.silabs.com/pcie-learningcenter.
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Rev. 1.4 | 5
