SL4020B
14 Stage Ripple-Carry Binary Counter/Divider
High-Voltage Silicon-Gate CMOS
The SL4020B is ripple-carry binary counter. All counter stages are
master-slave flip-flops. The state of a counter advances one count on
the negative transition of each input pulse; a high level on the RESET
line resets the counter to its all zeros state. Schmitt trigger action on the
input-pulse line permits unlimited rise and fall times.
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
SL4020BN Plastic
SL4020BD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
Clock
Reset
L
L
X
H
X=don’t care
Output
Output state
No change
Advance to
next state
All Outputs
are low
PIN 16 =V
CC
PIN 8 = GND
SLS
System Logic
Semiconductor
SL4020B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V ).
CC
Unused outputs must b e left open.
SLS
System Logic
Semiconductor
SL4020B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
IH
Parameter
Minimum High-Level
Input Voltage
Maximum Low -Level
Input Voltage
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
(per Package)
Minimum Output Low
(Sink) Current
Test Conditions
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
V
OUT
=0.5V or V
CC
- 0.5V
V
OUT
=1.0V or V
CC
- 1.0V
V
OUT
=1.5V or V
CC
- 1.5V
V
IN
=GND or V
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
Guaranteed Limit
≥-55°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
5
10
20
100
0.64
1.6
4.2
-2.0
-0.64
-1.6
-4.2
25°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±0.1
5
10
20
100
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
≤125
°C
3.5
7
11
1.5
3
4
4.95
9.95
14.95
0.05
0.05
0.05
±1.0
150
300
600
3000
0.36
0.9
2.4
mA
-1.15
-0.36
-0.9
-2.4
Unit
V
V
IL
V
V
OH
V
V
OL
V
IN
=GND or V
CC
V
I
IN
I
CC
V
IN
= GND or V
CC
V
IN
= GND or V
CC
µA
µA
I
OL
V
IN
= GND or V
CC
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
mA
I
OH
Minimum Output High V
IN
= GND or V
CC
(Source) Current
U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
SLS
System Logic
Semiconductor
SL4020B
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
f
max
Parameter
Maximum Clock Frequency(Figure 1)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
-
Guaranteed Limit
≥-55°C
3.5
8
12
360
160
130
330
80
60
280
120
100
200
100
80
25°C
3.5
8
12
360
160
130
330
80
60
280
120
100
200
100
80
7.5
≤125°C
1.75
4
6
720
320
260
660
160
120
560
240
200
400
200
160
Unit
MHz
t
PLH
, t
PHL
Maximum Propagation Delay, Clock to Q1
(Figure 1)
Maximum Propagation Delay, Q
n
to Q
n
+1 (Figure
3)
Maximum Propagation Delay, Reset to Any Q
(Figure 2)
Maximum Output Transition Time, Any Output
(Figure 1)
Maximum Input Capacitance
ns
t
PLH
, t
PHL
ns
t
PHL
ns
t
TLH
, t
THL
ns
C
IN
pF
TIMING REQUIREMENTS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
w
Parameter
Minimum Pulse Width, Clock (Figure 1)
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
Guaranteed Limit
≥-55°C
140
60
40
200
80
60
350
150
100
25°C
140
60
40
200
80
60
350
150
100
Unlimited
≤125°C
280
120
80
400
160
120
700
300
200
Unit
ns
t
w
Minimum Pulse Width, Reset (Figure 2)
ns
t
rem
Minimum Removal Time, Reset(Figure 2)
ns
t
r,
t
f
Maximum Input Rise and Fall Times, Clock
(Figure 1)
µs
SLS
System Logic
Semiconductor
SL4020B
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
SLS
System Logic
Semiconductor
