U4223B
Time-Code Receiver with A/D Converter
Description
The U4223B is a bipolar integrated straight-through receiver circuit in the frequency range of 40 kHz to 80 kHz.
The device is designed for radio-controlled clock applications.
Features
D
Very low power consumption
D
Very high sensitivity
D
High selectivity by using two crystal filters
D
Power-down mode available
D
Only a few external components necessary
D
4-bit digital output
D
AGC hold mode
Block Diagram
PON
VCC 1
GND
16
Power supply
3
9
Impulse
circuit
2
4
AGC
amplifier
5
6
14
15
Rectifier &
integrator
7
REC
8
INT
13
SL
CLK D3
12
17
D2
18
ADC
D1
19
D0
20
Decoder
11
10
FLB
FLA
DEC
IN
SB Q1A Q1B Q2A Q2B
Figure 1. Block diagram
Ordering and Package Information
Extended Type Number
U4223B-MFS
U4223B-MFSG3
T4223B-MF
T4223B-MC
Package
SSO20 plastic
SSO20 plastic
No
No
Remarks
Taping according to IEC-286-3
Die on foil
Die on carrier
Rev. A7, 06-Mar-01
1 (18)
U4223B
Pin Description
Pin
VCC
IN
GND
SB
Q1A
Q1B
1
2
3
4
5
20
19
18
17
16
D0 (LSB)
D1
D2
D3 (MSB)
PON
Q2B
Q2A
SL
CLK
FLB
1
2
3
4
5
6
7
8
9
10
15
14
13
12
11
11
12
REC
INT
DEC
FLA
7
8
9
10
13
14
15
16
17
18
19
20
Figure 2. Pinning
Symbol
VCC
IN
GND
SB
Q1A
Q1B
REC
INT
DEC
FLA
FLB
CLK
SL
Q2A
Q2B
PON
D3
D2
D1
D0
Function
Supply voltage
Amplifier – Input
Ground
Bandwidth control
Crystal filter 1
Crystal filter 1
Rectifier output
Integrator output
Decoder input
Lowpass filter
Lowpass filter
Clock input for ADC
AGC hold mode
Crystal filter 2
Crystal filter 2
Power ON/OFF control
Data out MSB
Data out
Data out
Data out LSB
U4223B
6
IN
A ferrite antenna is connected between IN and VCC. For
high sensitivity, the Q factor of the antenna circuit should
be as high as possible. Please note that a high Q factor
requires temperature compensation of the resonant
frequency in most cases. Specifications are valid for
Q>30. An optimal signal-to-noise ratio will be achieved
by a resonant resistance of 50 to 200 kW.
SB
A resistor R
SB
is connected between SB and GND. It
controls the bandwidth of the crystal filters. It is recom-
mended: R
SB
= 0
W
for DCF 77.5 kHz, R
SB
= 10 kW for
60 kHz WWVB and R
SB
= open for JG2AS 40 kHz.
VCC
SB
IN
GND
Figure 3.
Figure 4.
2 (18)
Rev. A7, 06-Mar-01
U4223B
Q1A, Q1B
In order to achieve a high selectivity, a crystal is con-
nected between the Pins Q1A and Q1B. It is used with the
serial resonant frequency of the time-code transmitter
(e.g., 60 kHz WWVB, 77.5 kHz DCF or 40 kHz JG2AS).
The equivalent parallel capacitor of the filter crystal is
internally compensated. The compensated value is about
0.7 pF. If full sensitivity and selectivity are not needed,
the crystal filter can be substituted by a capacitor of 82 pF.
SL
AGC hold mode: SL high (V
SL
= V
CC
) sets normal func-
tion, SL low (V
SL
= 0) disconnects the rectifier and holds
the voltage V
INT
at the integrator output and also the AGC
amplifier gain.
VCC
SL
Q1A
Q1B
Figure 8.
GND
Figure 5.
INT
Integrator output: The voltage V
INT
is the control voltage
for the AGC. The capacitor C
2
between INT and DEC
defines the time constant of the integrator. The current
through the capacitor is the input signal of the decoder.
REC
Rectifier output and integrator input: The capacitor C
1
between REC and INT is the lowpass filter of the rectifier
and at the same time a damping element of the gain
control.
INT
REC
GND
GND
Figure 6.
Figure 9.
FLA, FLB
DEC
Decoder input: Senses the current through the integration
capacitor C
2
. The dynamic input resistance has a value of
about 420 kW and is low compared to the impedance of
C
2
.
Lowpass filter: A capacitor C
3
connected between FLA
and FLB suppresses higher frequencies at the trigger
circuit of the decoder.
DEC
FLB
FLB
GND
Figure 7.
Figure 10.
94 8377
Rev. A7, 06-Mar-01
3 (18)
U4223B
Q2A, Q2B
According to Q1A/Q1B, a crystal is connected between
the Pins Q2A and Q2B. It is used with the serial resonant
frequency of the time-code transmitter (e.g., 60 kHz
WWVB, 77.5 kHz DCF or 40 kHz JG2AS). The equiva-
lent parallel capacitor of the filter crystal is internally
compensated. The value of the compensation is about
0.7 pF.
A sequence of the digitalized time-code signal can be
analyzed by a special noise-suppressing algorithm in
order to increase the sensitivity and the signal-to-noise
ratio (more than 10 dB compared to conventional
decoding). Details about the time-code format are
described separately.
Q2A
Q2B
GND
Figure 11.
PON
If PON is connected to GND, the receiver will be
activated. The set-up time is typically 0.5 s after applying
GND at this pin. If PON is connected to VCC, the receiver
will switch to power-down mode.
Decimal
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Gray
0000
0001
0011
0010
0110
0111
0101
0100
1100
1101
1111
1110
1010
1011
1001
1000
VCC
VCC
PON
D0 ... D3
PON
GND
Figure 12.
Figure 13.
CLK
D0, D1, D2, D3
The outputs of the ADC consist of PNP-NPN push-pull
stages and can be directly connected to a microcomputer.
In order to avoid any interference of the output into the
antenna circuit, we recommend terminating each digital
output with a capacitor of 10 nF. The digitalized signal of
the ADC is Gray coded (see table). It should be taken into
account that in power-down mode (PON = high), D0, D1,
D2 and D3 will be high.
4 (18)
The input of the ADC is switched to the AGC voltage by
the rising slope of the clock. When conversion time has
passed (about 1.8 ms at 25°C), the digitalized field-
strength signal is stored in the output registers D0 to D3
as long as the clock is high and can be read by a micro-
computer. The falling slope of the clock switches the
input of the ADC to the time-code signal. In the mean-
time, the digitalized time-code signal is stored in the
output registers D0 to D3 as long as the clock is low (see
figure 14).
Rev. A7, 06-Mar-01
U4223B
V
clk
mV
100
50
0
4
7 8
11 12 t/ms
Now, the time-code
signal can be read
Falling edge initiates
time-code conversion
Now, the AGC value can be read
Thus, the first step in designing the antenna circuit is to
measure the bandwidth. Figure 17 shows an example for
the test circuit. The RF signal is coupled into the bar
antenna by inductive means, e.g., a wire loop. It can be
measured by a simple oscilloscope using the 10:1 probe.
The input capacitance of the probe, typically about 10 pF,
should be taken into consideration. By varying the fre-
quency of the signal generator, the resonant frequency
can be determined.
Rising edge initiates
AGC signal conversion
Figure 14.
RF signal
generator
77.5 kHz
Scope
Probe
10 : 1
w10
MW
wire loop
C
res
In order to minimize interferences, we recommend a
voltage swing of about 100 mV. A full supply-voltage
swing is possible but reduces the sensitivity.
Figure 16.
VCC
CLK
At the point where the voltage of the RF signal at the
probe drops by 3 dB, the two frequencies can then be
measured. The difference between these two frequencies
is called the bandwidth BW
A
of the antenna circuit. As the
value of the capacitor C
res
in the antenna circuit is known,
it is easy to compute the resonant resistance according to
the following formula:
R
res
+
Figure 15.
GND
2
p
1
BW
A
C
res
Please note:
The signals and voltages at the Pins REC, INT, FLA,
FLB, Q1A, Q1B, Q2A and Q2B cannot be measured by
standard measurement equipment due to very high inter-
nal impedances. For the same reason, the PCB should be
protected against surface humidity.
where
R
res
is the resonant resistance,
BW
A
is the measured bandwidth (in Hz)
C
res
is the value of the capacitor in the antenna circuit
(in Farad).
If high inductance values and low capacitor values are
used, the additional parasitic capacitances of the coil
(v20 pF) must be considered. The Q value of the capa-
citor should be no problem if a high Q type is used. The
Q value of the coil differs more or less from the DC
resistance of the wire. Skin effects can be observed but do
not dominate.
Therefore, it should not be a problem to achieve the
recommended values of the resonant resistance. The use
of thicker wire increases the Q value and accordingly
reduces bandwidth. This is advantageous in order to
improve reception in noisy areas. On the other hand,
temperature compensation of the resonant frequency
might become a problem if the bandwidth of the antenna
circuit is low compared to the temperature variation of the
resonant frequency. Of course, the Q value can also be
reduced by a parallel resistor.
Design Hints for the Ferrite Antenna
The bar antenna is a very critical device of the complete
clock receiver. Observing some basic RF design rules
helps to avoid possible problems. The IC requires a reso-
nant resistance of 50 kW to 200 kW. This can be achieved
by a variation of the L/C-relation in the antenna circuit.
It is not easy to measure such high resistances in the RF
region. A more convenient way is to distinguish between
the different bandwidths of the antenna circuit and to cal-
culate the resonant resistance afterwards.
Rev. A7, 06-Mar-01
5 (18)
编程基础
