T48C510
MARC4 – 4-bit MTP Universal Microcontroller
The T48C510 is an Multi Time Programmable (MTP) microcontroller which is pin and functionally compatible to the
Atmel Wireless & Microcontrollers’ M44C510E mask programmable microcontroller. It contains EEPROM, RAM,
up to 34 digital I/O pins, up to 10 maskable external interrupt sources, 4 maskable internal interrupts, a watchdog timer,
interval timer, 2 x 8-bit multifunction timer/counter module and a versatile software configurable on-chip system clock
module.
Features / Benefits
D
Programmable system clock with prescaler and five
different clock sources:
– Up to 8-MHz crystal oscillator (system clock)
– 32-kHz crystal oscillator
– RC-oscillator fully integrated
– RC-oscillator with external resistor adjustment
– External clock input
D
Wide supply-voltage range (2.4 V to 6.2 V)
D
Very low halt current
D
4 KByte program EEPROM, 256 x 4-bit RAM
D
8 hard- and software interrupt priority levels
D
Up to 10 external and 4 internal interrupts, bitwise
maskable with programmable priority level
D
Up to 34 I/O lines
TE
SCLIN
OSCIN OSCOUT AVDD VSS
NRST
VDD TIM1
D
I/O ports – bitwise configurable with combined inter-
rupt handling (for serial I/O applications)
D
2 x 8-bit multifunction timer/counters
D
Coded reset and watchdog timer
D
Power-on reset and “brown out” function
D
Various power-down modes
D
Efficient, hardware-controlled interrupt handling
D
High-level programming language in qFORTH
D
Comprehensive library of useful routines
D
Windows 95/NT based development and programmer
tools
Config.
EEPROM
Test
Sleep
System
clock
Real time
clock
Master
reset
EEPROM
4K x 8 bit
RAM
256 x 4 bit
Timer/
counter
Watch–
dog
Prescaler
Timer 1
Timer 0
Melody
& buzzer
MARC4
4-bit CPU core
I/O bus
I/O
I/O
4
4
4
I/O
I/O
4
I/O
Interrupt
& reset
4
I/O
Interrupt
4
I/O I/O
Interrupt
4
2
I/O
4
PM
Port 0 Port 1 Port 5 Port 7
Port A
Port B
Port C
Port 6
Port 4
16536
Figure 1. Block diagram
Rev. A2, 26-Feb-01
1 (61)
Preliminary Information
T48C510
Ordering Information
Extended Type Number
T48C510 – ILS
T48C510 – ILQ
BP70
BP71
Package
SSO44
SSO44
OSCIN
AVDD
SCLIN
BPC3
BPC2
BPB3
BPB2
BPB1
BPB0
BP72
BP73
BP61
BP60
Remarks
Stick
Taped and reeled
OSCOUT
NRST
BPA0
BPA1
BPA2
21
BP11
24
BPA3
BP10
22
23
44
43
42
41
40
PM
39
38
37
36
35
34
33
32
31
30
29
28
27
26
19
BP13
T48C510
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
BPC1 16
17
BPC0 18
V SS
TIM1
BP53
BP52
BP51
BP50
BP43
BP42
BP41
BP40
BP03
BP02
BP01
BP00
Figure 2. Pin connections SSO44-package
Table 1 Pin description
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Á
Á
Á
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Á
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ÁÁÁÁÁÁ
Name
V
DD
V
SS
Function
Power supply voltage +2.4 V to +6.2 V
Circuit ground
AV
DD
Analog power supply voltage +2.4 V to +6.2 V
BP00 – BP03
BP10 – BP13
BP50 – BP53
BP70 – BP73
4 I/O lines of Port 0 – automatic nibblewise configurable / programmer interface
4 I/O lines of Port 1 – automatic nibblewise configurable
4 I/O lines of high current Port 5 – bitwise configurable
4 I/O lines of high current Port 7 – bitwise configurable
BPA0 – BPA3
4 I/O lines of Port A – bitwise configurable, as inputs to a port monitor module and optional
coded reset inputs
4 I/O lines of Port B – bitwise configurable I/O and as inputs to a port monitor module
4 I/O lines of Port C – bitwise configurable I/O
2 I/O lines of Port 6 – bitwise configurable I/O or as external programmable interrupts
I/O line BP40 of Port 4 – configurable or timer/counter I/O T0OUT0
I/O line BP41 of Port 4 – configurable or timer/counter I/O T0OUT1
BPB0 – BPB3
BPC0 – BPC3
BP60 – BP61
BP40 (T0OUT0)
BP41 (T0OUT1)
BP42 (BUZ)
TIM1
BP43 (NBUZ)
SCLIN
High current I/O line BP42 of Port 4 – configurable or buzzer output BUZ
Dedicated I/O for Timer 1
High current I/O line BP43 of Port 4 – configurable or buzzer output NBUZ
External trimming resistor or external clock input
OSCIN
TE
32-kHz quartz crystal or 4-MHz quartz crystal input pin
OSCOUT
NRST
PM
32-kHz quartz crystal or 4-MHz quartz crystal output pin
Testmode input, used to control the production test modes (internal pull-down)
Reset input (/output), a logic low on this pin resets the device. An internal watchdog or
coded reset can cause a low pulse on this pin.
MTP program mode enable pin (internal pull-down)
2 (61)
BP12
VDD
TE
20
25
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
Table of Contents
1
MARC4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2
Components of MARC4 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.2
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.3
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.4
ALU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.5
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.6
I/O Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3
Interrupt Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.1
Hardware Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3.2
Software Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4
Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5
Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.1
Clock Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.2
Oscillator Circuits and External Clock Input Stage . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 1 Fully Integrated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RC-Oscillator 2 with External Trimming Resistor . . . . . . . . . . . . . . . . . . . . . . . . .
4-MHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32-kHz Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Quartz Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.3
Clock Management Register (CM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Configuration Register (SC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.4
Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5.5
Clock Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peripheral Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1
Addressing Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2
Bidirectional Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1
Bidirectional Port 0 and Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.2
Bidirectional Port 5, Port 7 and Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3
Bidirectional Port A and Port B with Port Monitor Function . . . . . . . . . . . . . . . .
2.2.4
Bidirectional Port 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.5
Bidirectional Port 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.6
TIM1 – Dedicated Timer 1 I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3
Interval Timers / Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1
Interval Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5
Timer/Counter Module (TCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.1
General Timer/Counter Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.2
Timer/Counter in 16-bit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.3
Timer 0 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5.4
Timer 1 Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5
5
5
5
6
6
9
9
9
9
11
11
12
13
13
14
14
14
14
15
15
15
16
16
17
17
18
18
21
22
23
23
25
27
28
28
29
30
30
32
35
35
44
2
Rev. A2, 26-Feb-01
3 (61)
Preliminary Information
T48C510
Table of Contents (continued)
2.6
2.7
2.8
Buzzer Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MTP Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Noise Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1
Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2
Electromagnetic Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2
DC Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1
Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Hardware Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
49
50
50
51
51
51
51
53
57
57
58
59
3
4
5
4 (61)
Rev. A2, 26-Feb-01
Preliminary Information
T48C510
1
MARC4 Architecture
Reset
Reset
Clock
System
clock
Sleep
1.1
General Description
The functionality, programming and pinning of the
T48C510 is compatible with the M44C510E mask pro-
grammable microcontroller from Atmel Wireless &
Microcontrollers. All on-chip modules are addressed and
controlled with exactly the same programming code, so
that a program targeted for the M44C510E can be read
directly into the T48C510 and will operate in the same
fashion.
The MARC4 microcontroller consists of an advanced
stack based 4-bit CPU core and on-chip peripherals. The
CPU is based on the HARVARD architecture with physi-
cally separate program memory (EEPROM) and data
memory (RAM). Three independent buses, the instruc-
tion bus, the memory bus and the I/O bus are used for
parallel communication between EEPROM, RAM and
peripherals. This enhances program execution speed by
allowing both instruction prefetching, and a simultaneous
communication to the on-chip peripheral circuitry. The
Rev. A2, 26-Feb-01
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MARC4 CORE
PC
X
Y
SP
RP
Program
memory
RAM
256 x 4-bit
Instruction
bus
Instruction
decoder
Interrupt
controller
Memory bus
TOS
CCR
ALU
I/O bus
On–chip peripheral modules
Figure 3. MARC4 core
94 8973
extremely powerful integrated interrupt controller with
associated eight prioritized interrupt levels supports fast
and efficient processing of hardware events. The MARC4
is designed for the high-level programming language
qFORTH. The core includes an expression and a return
stack. This architecture allows high-level language pro-
gramming without any loss in efficiency or code density.
1.2
Components of MARC4 Core
The core contains EEPROM, RAM, ALU, a program
counter, RAM address registers, an instruction decoder
and an interrupt controller. The following sections de-
scribe each functional block in more detail:
1.2.1
EEPROM
The program memory (EEPROM) is programmed with
the customer application program. The EEPROM is ad-
dressed by a 12-bit wide program counter, thus
predefining a maximum program bank size of 4 Kbytes.
5 (61)
Preliminary Information
FPGA/CPLD
