CPU to SDRAM Skew (@ 133 MHz) ....................... ± 0.5 ns
CPU to SDRAM Skew (@ 100 MHz) ................. 4.5 to 5.5 ns
CPU to 3V66 Skew (@ 66 MHz)........................ 7.0 to 8.0 ns
3V66 to PCI Skew (3V66 lead) .......................... 1.5 to 3.5 ns
PCI to APIC Skew..................................................... ± 0.5 ns
Block Diagram
VDDQ3
REF2X/FS3
PLL REF FREQ
Pin Configuration
[1]
GND
VDDQ3
REF2X/FS3^
X1
X2
VDDQ3
3V66_0
3V66_1
3V66_2
GND
PCI0/FS0^
PCI1/FS1^
PCI2/FS2^
GND
PCI3
PCI4
VDDQ3
PCI5
PCI6
PCI7
GND
48MHz
48MHz/FS4^
24_48MHz/SEL24_48MHz#*
VDDQ3
SDATA
GND
VDDQ3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDQ2
APIC
GND
VDDQ2
CPU0
CPU1
GND
SDRAM0
SDRAM1
SDRAM2
VDDQ3
GND
SDRAM3
SDRAM4
SDRAM5
SDRAM6
VDDQ3
GND
SDRAM7
SDRAM8
SDRAM9
SDRAM10
VDDQ3
GND
SDRAM11
SDRAM12
RST#
SCLK
X1
X2
XTAL
OSC
VDDQ2
SDATA
SCLK
SMBus
Logic
Divider,
Delay,
and
Phase
Control
Logic
CPU0:1
2
W305B
APIC
VDDQ3
3
(FS0:4)
3V66_0:2
PCI0/FS0
PCI1/FS1
PCI2/FS2
5
13
PLL 1
PCI3:7
SDRAM0:12
RST#
VDDQ3
48MHz
PLL2
/2
48MHz/FS4
24_48MHz/SEL24_48MHz#
1. Internal 100K pull-up and 100K pull-down resistors present on inputs marked with * and ^ respectively. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH or LOW.
Cypress Semiconductor Corporation
Document #: 38-07262 Rev. *B
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised September 1, 2004
W305B
Pin Definitions
Pin Name
REF2X/FS3
Pin No.
3
Pin
Type
I/O
Pin Description
Reference Clock with 2x Drive/Frequency Select 3.
3.3V 14.318-MHz clock
output. This pin also serves as the select strap to determines device operating
frequency as described in
Table 5.
Crystal Input.
This pin has dual functions. It can be used as an external
14.318-MHz crystal connection or as an external reference frequency input.
Crystal Output.
An input connection for an external 14.318-MHz crystal
connection. If using an external reference, this pin must be left unconnected.
PCI Clock 0/Frequency Selection 0.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 1/Frequency Selection 1.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 2/Frequency Selection 2.
3.3V 33-MHz PCI clock outputs. This pin
also serves as the select strap to determine device operating frequency as
described in
Table 5.
PCI Clock 3 through 7.
3.3V 33-MHz PCI clock outputs. PCI0:7 can be individ-
ually turned off via SMBus interface.
66-MHz Clock Output.
3.3V output clocks. The operating frequency is
controlled by FS0:4 (see
Table 5).
48MHz.
3.3V 48-MHz non-spread spectrum output.
48-MHz Output/Frequency Selection 4.
3.3V 48-MHz non-spread spectrum
output. This pin also serves as the select strap to determine device operating
frequency as described in
Table 5.
24- or 48-MHz Output/Select 24 or 48MHz.
3.3V 24 or 48-MHz non-spread
spectrum output. This pin also serves as the select strap to determine the output
frequency for 24_48MHz output.
X1
X2
PCI0/FS0
4
5
11
I
O
I/O
PCI1/FS1
12
I/O
PCI2/FS2
13
I/O
PCI3:7
3V66_0:2
48MHz
48MHz/FS4
15, 16, 18, 19, 20
7, 8, 9
22
23
O
O
O
I/O
24_48MHz/SEL24
_48MHz#
RST#
24
I/O
30
O
Reset#.
Open-drain RESET# output.
(open-d
rain)
O
CPU Clock Outputs.
Clock outputs for the host bus interface. Output
frequencies depending on the configuration of FS0:4. Voltage swing is set by
VDDQ2.
SDRAM Clock Outputs.
3.3V outputs for SDRAM and chipset. The operating
frequency is controlled by FS0:4 (see
Table 5).
Synchronous APIC Clock Outputs.
Clock outputs running synchronous with
the PCI clock outputs. Voltage swing set by VDDQ2.
Data pin for SMBus circuitry.
Clock pin for SMBus circuitry.
3.3V Power Connection.
Power supply for SDRAM output buffers, PCI output
buffers, reference output buffers and 48-MHz output buffers. Connect to 3.3V.
2.5V Power Connection.
Power supply for APIC and CPU output buffers.
Connect to 2.5V.
Ground Connections.
Connect all ground pins to the common system ground
plane.
CPU0:1
52, 51
SDRAM0:12,
49, 48, 47, 44,
43, 42, 41, 38,
37, 36, 35, 32, 31
55
26
29
2, 6, 17, 25, 28,
34, 40, 46
53, 56
1, 10, 14, 21, 27,
33, 39, 45, 50, 54
O
O
I/O
I
P
P
G
APIC
SDATA
SCLK
VDDQ3
VDDQ2
GND
Document #: 38-07262 Rev. *B
Page 2 of 21
W305B
Output Strapping Resistor
Series Termination Resistor
W305B
Power-on
Reset
Timer
Output
Buffer
Output Three-state
Q
Clock Load
Hold
Output
Low
D
10 kΩ
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Overview
The W305B is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel
®
archi-
tecture platform using graphics integrated core logic.
Functional Description
I/O Pin Operation
Upon power-up the power on strap option pins act as a logic
input. An external 10-kΩ strapping resistor should be used.
Figure 1
shows a suggested method for strapping resistor
connections.
0 ns
10 ns
20 ns
After 2 ms, the pin becomes an output. Assuming the power
supply has stabilized by then, the specified output frequency
is delivered on the pins. If the power supply has not yet
reached full value, output frequency initially may be below
target but will increase to target once supply voltage has stabi-
lized. In either case, a short output clock cycle may be
produced from the CPU clock outputs when the outputs are
enabled.
Offsets Among Clock Signal Groups
Figure 2, Figure 3,
and
Figure 4
represent the phase
relationship among the different groups of clock outputs from
W305B under different frequency modes.
30 ns
40 ns
CPU 66-MHz
CPU 66 Period
SDRAM 100-MHz
SDRAM 100 Period
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC 16.6-MHz
Hub-PCI
Figure 2. Group Offset Waveforms (66-MHz CPU Clock, 100-MHz SDRAM Clock)
Document #: 38-07262 Rev. *B
Page 3 of 21
W305B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 100-MHz
CPU 100 Period
SDRAM 100 Period
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
REF 14.318-MHz
USB 48-MHz
APIC16.6-MHz
Hub-PC
Figure 3. Group Offset Waveforms (100-MHz CPU Clock, 100-MHz SDRAM Clock)
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 133-MHz
Cycle Repeats
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC 16.6-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM)
Document #: 38-07262 Rev. *B
Page 4 of 21
W305B
0 ns
10 ns
20 ns
30 ns
40 ns
CPU 133-MHz
Cycle Repeat
SDRAM 133MHz
3V66 66-MHz
PCI 33-MHz
APIC 16.6-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 5. Group Offset Waveform (133-MHz CPU/133-MHz SDRAM)
Serial Data Interface
The W305B features a two-pin, serial data interface that can
be used to configure internal register settings that control
particular device functions.
Data Protocol
The clock driver serial protocol supports byte/word write,
byte/word read, block write and block read operations from the
Table 1. Command Code Definition
Bit
7
6:0
Descriptions
0 = Block read or block write operation
1 = Byte/Word read or byte/word write operation
Byte offset for byte/word read or write operation. For block read or write operations, these bits
need to be set at ‘0000000’.
controller. For block write/read operation, the bytes must be
accessed in sequential order from lowest to highest byte with
the ability to stop after any complete byte has been trans-
ferred. For byte/word write and byte read operations, system
controller can access individual indexed byte. The offset of the
