A
PPLICATION
N
OTE
A V A I L A B L E
AN95 • AN103 • AN107
16K/64K
X84161/641
µPort Saver EEPROM
DESCRIPTION
MPS
™
EEPROM
FEATURES
• Up to 10MHz data transfer rate
• 25ns Read Access Time
• Direct interface to microprocessors and micro-
controllers
—Eliminates I/O port requirements
—No interface glue logic required
—Eliminates need for parallel to serial converters
• Low power CMOS
—2.5V–5.5V and 5V
±
10% versions
—Standby current less than 1µA
—Active current less than 1mA
• Byte or page write capable
—32-byte page write mode
• Typical nonvolatile write cycle time: 2ms
• High reliability
—100,000 endurance cycles
—Guaranteed data retention: 100 years
• Small packages options
—8-lead mini-DIP package
—8-lead SOIC package
—8, 20-lead TSSOP package
The µPort Saver memories need no serial ports or
special hardware and connect to the processor mem-
ory bus. Replacing bytewide data memory, the µPort
Saver uses bytewide memory control functions, takes
a fraction of the board space and consumes much less
power. Replacing serial memories, the µPort Saver
provides all the serial benefits, such as low cost, low
power, low voltage, and small package size, while
releasing I/Os for more important uses.
The µPort Saver memory outputs data within 25ns of
an active read signal. This is less than the read access
time of most hosts and provides “no-wait-state” opera-
tion. This prevents bottlenecks on the bus. With rates
to 10MHz, the µPort Saver supplies data faster than
required by most host read cycle specifications. This
eliminates the need for software NOPs.
The µPort Saver memories communicate over one line
of the data bus using a sequence of standard bus read
and write operations. This “bit serial” interface allows
the µPort Saver to work well in 8-bit, 16-bit, 32-bit, and
64-bit systems.
A Write Protect (WP) pin prevents inadvertent writes to
the memory.
Xicor EEPROMs are designed and tested for applica-
tions requiring extended endurance. Inherent data
retention is greater than 100 years.
BLOCK DIAGRAM
Internal Block Diagram
System Connection
µP
µC
DSP
ASIC
RISC
D
0
Ports
Saved
P0/CS
P1/CLK
P2/DI
P3/DO
OE
WE
Y Decode
Data Register
A
15
A
0
D
7
WP
MPS
H.V. Generation
Timing & Control
CE
I/O
OE
WE
Command
Decode
and
Control
Logic
EEPROM
Array
X
DEC
8K x 8
2K x 8
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Characteristics subject to change without notice.
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X84161/641
PIN CONFIGURATIONS
8-Lead PDIP/SOIC
CE
I/O
WP
V
SS
8
1
2
X84161
7
3
X84641
6
4
5
V
CC
NC
OE
WE
NC
V
CC
CE
I/O
1
2
3
4
8-Lead TSSOP
X84161
8
7
6
5
OE
WE
WP
V
SS
NC
NC
CE
I/O
NC
NC
NC
WP
V
SS
NC
20-Lead TSSOP
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
NC
NC
V
CC
NC
NC
NC
NC
OE
WE
NC
X84641
PIN NAMES
Pin
I/O
CE
OE
WE
WP
V
CC
V
SS
NC
Description
Data Input/Output
Chip Enable Input
Output Enable Input
Write Enable Input
Write Protect Input
Supply Voltage
Ground
No Connect
Write Enable (WE)
The Write Enable input must be LOW to write either
data or command sequences to the device.
Data In/Data Out (I/O)
Data and command sequences are serially written to
or serially read from the device through the I/O pin.
Write Protect (WP)
When the Write Protect input is LOW, nonvolatile writes
to the device are disabled. When WP is HIGH, all func-
tions, including nonvolatile writes, operate normally. If a
nonvolatile write cycle is in progress, WP going LOW
will have no effect on the cycle already underway, but
will inhibit any additional nonvolatile write cycles.
DEVICE OPERATION
The X84161/641 are serial EEPROMs designed to
interface directly with most microprocessor buses.
Standard CE, OE, and WE signals control the read and
write operations, and a single l/O line is used to send
and receive data and commands serially.
Data Timing
Data input on the l/O line is latched on the rising edge
of either WE or CE, whichever occurs first. Data output
on the l/O line is active whenever both OE and CE are
LOW. Care should be taken to ensure that WE and OE
are never both LOW while CE is LOW.
Read Sequence
A read sequence consists of sending a 16-bit address
followed by the reading of data serially. The address is
written by issuing 16 separate write cycles (WE and
CE LOW, OE HIGH) to the part without a read cycle
between the write cycles. The address is sent serially,
PACKAGE SELECTION GUIDE
84161
8-Lead PDIP
8-Lead SOIC
8-Lead TSSOP
8-Lead XBGA
8-Lead PDIP
8-Lead SOIC
20-Lead TSSOP
84641
PIN DESCRIPTIONS
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When CE is HIGH, the chip is dese-
lected, the I/O pin is in the high impedance state, and
unless a nonvolatile write operation is underway, the
device is in the standby power mode.
Output Enable (OE)
The Output Enable input must be LOW to enable the
output buffer and to read data from the device on the I/O
line.
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Characteristics subject to change without notice.
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X84161/641
most significant bit first, over the I/O line. Note that this
sequence is fully static, with no special timing restric-
tions, and the processor is free to perform other tasks
on the bus whenever the device CE pin is HIGH. Once
the 16 address bits are sent, a byte of data can be read
on the I/O line by issuing 8 separate read cycles (OE
and CE LOW, WE HIGH). At this point, writing a ‘1’ will
terminate the read sequence and enter the low power
standby state, otherwise the device will await further
reads in the sequential read mode.
Sequential Read
The byte address is automatically incremented to the
next higher address after each byte of data is read.
The data stored in the memory at the next address can
be read sequentially by continuing to issue read
cycles. When the highest address in the array is
reached, the address counter rolls over to address
$0000 and reading may be continued indefinitely.
Figure 1. Read Sequence
Reset Sequence
The reset sequence resets the device and sets an
internal write enable latch. A reset sequence can be
sent at any time by performing a read/write “0”/read
operation (see Figs. 1 and 2). This breaks the multiple
read or write cycle sequences that are normally used
to read from or write to the part. The reset sequence
can be used at any time to interrupt or end a sequential
read or page load. As soon as the write “0” cycle is
complete, the part is reset (unless a nonvolatile write
cycle is in progress). The second read cycle in this
sequence, and any further read cycles, will read a
HIGH on the l/O pin until a valid read sequence (which
includes the address) is issued. The reset sequence
must be issued at the beginning of both read and write
sequences to be sure the device initiates these opera-
tions properly.
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
I/O (OUT)
RESET
When Accessing: X84161 Array: A15–A11=0
X84641 Array: A15–A13=0
Load Address
D7 D6 D5 D4 D3 D2 D1 D0
Read Data
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Characteristics subject to change without notice.
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X84161/641
Figure 2. Write Sequence
CE
OE
WE
I/O (IN)
"0"
A15 A14 A13 A12 A11 A10 A9 A8
A7 A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
"1"
"0"
I/O (OUT)
RESET
When Accessing: X84161 Array: A15–A11=0
X84641 Array: A15–A13=0
Load Address
Load Data
START
Nonvolatile
Write
Write Sequence
A nonvolatile write sequence consists of sending a
reset sequence, a 16-bit address, up to 32 bytes of
data, and then a special “start nonvolatile write cycle”
command sequence.
The reset sequence is issued first (as described in the
Reset Sequence section) to set an internal write
enable latch. The address is written serially by issuing
16 separate write cycles (WE and CE LOW, OE HIGH)
to the part without any read cycles between the writes.
The address is sent serially, most significant bit first, on
the l/O pin. Up to 32 bytes of data are written by issu-
ing a multiple of 8 write cycles. Again, no read cycles
are allowed between writes.
The nonvolatile write cycle is initiated by issuing a spe-
cial read/write “1”/read sequence. The first read cycle
ends the page load, then the write “1” followed by a
read starts the nonvolatile write cycle. The device rec-
ognizes 32-byte pages (e.g., beginning at addresses
XXXXXX00000 for X84161).
When sending data to the part, attempts to exceed the
upper address of the page will result in the address
counter “wrapping-around” to the first address on the
page, where data loading can continue. For this rea-
son, sending more than 256 consecutive data bits will
result in overwriting previous data.
A nonvolatile write cycle will not start if a partial or
incomplete write sequence is issued. The internal write
enable latch is reset when the nonvolatile write cycle is
completed and after an invalid write to prevent inad-
vertent writes. Note that this sequence is fully static,
with no special timing restrictions. The processor is
free to perform other tasks on the bus whenever the
chip enable pin (CE) is HIGH.
Nonvolatile Write Status
The status of a nonvolatile write cycle can be deter-
mined at any time by simply reading the state of the l/O
pin on the device. This pin is read when OE and CE
are LOW and WE is HIGH. During a nonvolatile write
cycle the l/O pin is LOW. When the nonvolatile write
cycle is complete, the l/O pin goes HIGH. A reset
sequence can also be issued during a nonvolatile write
cycle with the same result: I/O is LOW as long as a
nonvolatile write cycle is in progress, and l/O is HIGH
when the nonvolatile write cycle is done.
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X84161/641
Low Power Operation
The device enters an idle state, which draws minimal
current when:
– an illegal sequence is entered. The following are the
more common illegal sequences:
• Read/Write/Write—any time
• Read/Write ‘1’—When writing the address or writing
data.
• Write ‘1’—when reading data
• Read/Read/Write ‘1’—after data is written to
device, but before entering the NV write sequence.
– the device powers-up;
– a nonvolatile write operation completes.
While a sequential read is in progress, the device
remains in an active state. This state draws more cur-
rent than the idle state, but not as much as during a
read itself. To go back to the lowest power condition, an
invalid condition is created by writing a ‘1’ after the last
bit of a read operation.
Write Protection
The following circuitry has been included to prevent
inadvertent nonvolatile writes:
– The internal Write Enable latch is reset upon power-up.
– A reset sequence must be issued to set the internal
write enable latch before starting a write sequence.
– A special “start nonvolatile write” command
sequence is required to start a nonvolatile write
cycle.
– The internal Write Enable latch is reset automatically
at the end of a nonvolatile write cycle.
– The internal Write Enable latch is reset and remains
reset as long as the WP pin is LOW, which blocks all
nonvolatile write cycles.
– The internal Write Enable latch resets on an invalid
write operation.
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Characteristics subject to change without notice.
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