11
QPRO Family of XC1700E
Configuration PROMs
DS670 (v1.0) December 3, 2010
Product Specification
Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams of
Xilinx FPGA devices
On-chip address counter, incremented by each rising
edge on the clock input
Simple interface to the FPGA requires only one user
I/O pin
Cascadable for storing longer or multiple bitstreams
Programmable reset polarity (active High or active
Low) for compatibility with different FPGA solutions
Low-power CMOS EPROM process
Available in 5V version only
Programming support by leading programmer
manufacturers.
Design support using the Xilinx Alliance and
Foundation series software packages
Description
The XC1700E QPRO™ family of configuration PROMs
provide an easy-to-use, cost-effective method for storing
Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after the rising clock edge, data appears on the PROM
DATA output pin that is connected to the FPGA D
IN
pin. The
FPGA generates the appropriate number of clock pulses to
complete the configuration. Once configured, it disables the
PROM. When the FPGA is in Slave Serial mode, the PROM
and the FPGA must both be clocked by an incoming signal.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family.
For device programming, either the Xilinx Alliance™ or the
Foundation™ series development systems compiles the
FPGA design file into a standard HEX format which is then
transferred to most commercial PROM programmers.
•
•
•
•
•
•
•
•
X-Ref Target - Figure 1
V
CC
V
PP
GND
RESET/OE
or
OE/RESET
CE
CEO
CLK
Address Counter
TC
EPROM
Cell
Matrix
Output
OE
DATA
DS670_01_112910
Figure 1:
Simplified Block Diagram (Does Not Show Programming Circuit)
© Copyright 2010 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS670 (v1.0) December 3, 2010
Product Specification
www.xilinx.com
1
QPRO Family of XC1700E Configuration PROMs
Pin Description
DATA
Data output, 3-stated when either CE or OE are inactive. During programming, the DATA pin is I/O.
Note:
OE can be programmed to be either active High or active Low.
CLK
Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and 3-states the DATA output. The polarity of this input pin is
programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at zero, and the
DATA output is put in a high-impedance state. The polarity of this input is programmable. The default is active High RESET,
but the preferred option is active Low RESET, because it can be driven by the FPGA’s INIT pin.
The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different methods to invert this pin.
CE
When High, this pin disables the internal address counter, 3-states the DATA output, and forces the device into low-I
CC
standby mode.
CEO
Chip enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE
and OE inputs are both active AND the internal address counter has been incremented beyond its terminal count (TC) value.
In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO
stays High until the PROM is reset.
Note:
OE can be programmed to be either active High or active Low.
V
PP
Programming voltage. No overshoot above the specified maximum voltage is permitted on this pin. For normal read
operation, this pin
must
be connected to V
CC
. Failure to do so can lead to unpredictable, temperature-dependent operation
and severe problems. Do not leave V
PP
floating!
V
CC
and GND
V
CC
is positive supply pin and GND is ground pin.
DS670 (v1.0) December 3, 2010
Product Specification
www.xilinx.com
2
QPRO Family of XC1700E Configuration PROMs
PROM Pinouts
Table 1:
PROM Pinouts
Pin Name
DATA
CLK
RESET/OE (OE/RESET)
CE
GND
CEO
V
PP
V
CC
Pin Number
1
2
3
4
5
6
7
8
Capacity
Table 2:
Capacity
Devices
XC1765E
XC17256E
Configuration Bits
65,536
262,144
Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Table 3:
Number of Configuration Bits, Including Header, for Xilinx FPGAs and Compatible PROMs
Device
XC3000/A series
XC4000 series
XQ4005E
XQ4010E
XQ4013E
Configuration Bits
14,819 to 94,984
95,008 to 247,968
95,008
178,144
247,968
PROM
XC1765E to XC17256E
XC17256E
XC17256E
XC17256E
XC17256E
Controlling PROMs
Connecting the FPGA device with the PROM.
•
•
•
•
The DATA output(s) of the PROM(s) drives the D
IN
input of the lead FPGA device.
The Master FPGA CCLK output drives the CLK input(s) of the PROM(s).
The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any).
The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures
that the PROM address counter is reset before the start of any reconfiguration, even when a reconfiguration is initiated
by a V
CC
glitch. Other methods—such as driving RESET/OE from LDC or system reset—assume the PROM internal
power-on-reset is always in step with the FPGA’s internal power-on-reset. This might not be a safe assumption.
The PROM CE input can be driven from either the LDC or DONE pins. Using LDC avoids potential contention on the
D
IN
pin.
The CE input of the lead (or only) PROM is driven by the DONE output of the lead FPGA device, provided that DONE
is not permanently grounded. Otherwise, LDC can be used to drive CE, but must then be unconditionally High during
user operation. CE can also be permanently tied Low, but this keeps the DATA output active and causes an
unnecessary supply current of 10 mA maximum.
•
•
DS670 (v1.0) December 3, 2010
Product Specification
www.xilinx.com
3
QPRO Family of XC1700E Configuration PROMs
FPGA Master Serial Mode Summary
The I/O and logic functions of the configurable logic block (CLB) and their associated interconnections are established by a
configuration program. The program is loaded either automatically upon power up, or on command, depending on the state
of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an
external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode.
Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select
pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is
provided by the rising edge of the temporary signal CCLK, which is generated during configuration.
Master Serial Mode provides a simple configuration interface. Only a serial data line and two control lines are required to
configure an FPGA. Data from the PROM is read sequentially, accessed via the internal address and bit counters which are
incremented on every valid rising edge of CCLK.
If the user-programmable, dual-function D
IN
pin on the FPGA is used only for configuration, it must still be held at a defined
level during normal operation. Xilinx FPGAs take care of this automatically with an on-chip default pull-up resistor.
Programming the FPGA With Counters Unchanged Upon Completion
When multiple FPGA-configurations for a single FPGA are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and configuration begins with the first program stored in memory. Since
the OE pin is held Low, the address counters are left unchanged after configuration is complete. Therefore, to reprogram the
FPGA with another program, the DONE line is pulled Low and configuration begins at the last value of the address counters.
This method fails if a user applies RESET during the FPGA configuration process. The FPGA aborts the configuration and
then restarts a new configuration, as intended, but the PROM does not reset its address counter, since it never saw a High
level on its OE input. The new configuration, therefore, reads the remaining data in the PROM and interprets it as preamble,
length count etc. Since the FPGA is the master, it issues the necessary number of CCLK pulses, up to 16 million (2
24
) and
DONE goes High. However, the FPGA configuration will be completely wrong, with potential contentions inside the FPGA
and on its output pins. This method must, therefore, never be used when there is any chance of external reset during
configuration.
Cascading Configuration PROMs
For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded
PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts
its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its
DATA output. See
Figure 2.
After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA RESET pin goes Low,
assuming the PROM reset polarity option has been inverted.
To reprogram the FPGA with another program, the DONE line goes Low and configuration begins where the address
counters had stopped. In this case, avoid contention between DATA and the configured I/O use of D
IN
.
DS670 (v1.0) December 3, 2010
Product Specification
www.xilinx.com
4
QPRO Family of XC1700E Configuration PROMs
X-Ref Target - Figure 2
V
CC
D
OUT
OPTIONAL
Daisy-chained
FPGAs with
Different
configurations
OPTIONAL
Slave
FPGAs
with Identical
Configurations
V
CC
FPGA
MODES
(1)
3.3V
4.7KΩ
DATA
V
CC
V
PP
D
IN
DATA
RESET
RESET
PROM
CLK
CE
OE/RESET
CEO
CCLK
DONE
INIT
CLK
CE
Cascaded
Serial
Memory
OE/RESET
CCLK
(Output)
D
IN
D
OUT
(Output)
Notes:
1. For mode pin connections, refer to the
appropriate
FPGA data
sheet.
2. The one-time-programmable PROM
supports automatic
loading of configuration programs.
3.
Multiple devices can
be
cascaded to
support additional
FPGAs.
4. An early DONE inhibits the PROM data output one CCLK cycle
before
the FPGA I/Os
become active.
ds670_02_120210
Figure 2:
Master Serial Mode
DS670 (v1.0) December 3, 2010
Product Specification
www.xilinx.com
5
