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INTEGRATED CIRCUITS

DATA SHEET

For a complete data sheet, please also download:

•

The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•

The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT112

Dual JK flip-flop with set and reset;

negative-edge trigger

Product speciﬁcation

Supersedes data of December 1990

File under Integrated Circuits, IC06

1998 Jun 10

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with set and reset;

negative-edge trigger

FEATURES

•

Asynchronous set and reset

•

Output capability: standard

•

category: flip-flops

GENERAL DESCRIPTION

The 74HC/HCT112 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT112 are dual negative-edge triggered

JK-type flip-flops featuring individual nJ, nK, clock (nCP),

set (nS

) and reset (nR

) inputs.

QUICK REFERENCE DATA

GND = 0 V; T

amb

= 25

°C;

= t

= 6 ns

74HC/HCT112

The set and reset inputs, when LOW, set or reset the

outputs as shown in the function table regardless of the

levels at the other inputs.

A HIGH level at the clock (nCP) input enables the nJ and

nK inputs and data will be accepted. The nJ and nK inputs

control the state changes of the flip-flops as shown in the

function table. The nJ and nK inputs must be stable one

set-up time prior to the HIGH-to-LOW clock transition for

predictable operation.

Output state changes are initiated by the HIGH-to-LOW

transition of nCP.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

TYPICAL

SYMBOL

PHL

/ t

PLH

PARAMETER

propagation delay

nCP to nQ, nQ

to nQ, nQ

max

Notes

1. C

is used to determine the dynamic power dissipation (P

µW):

= C

CC2

+ ∑

CC2

) where:

= input frequency in MHz

= output frequency in MHz

∑

CC2

) = sum of outputs

= output load capacitance in pF

= supply voltage in V

2. For HC the condition is V

= GND to V

For HCT the condition is V

= GND to V

−

1.5 V

maximum clock frequency

input capacitance

power dissipation capacitance per ﬂip-ﬂop notes 1 and 2

CONDITIONS

= 15 pF; V

= 5 V

3.5

MHz

HCT

UNIT

1998 Jun 10

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with set and reset;

negative-edge trigger

ORDERING INFORMATION

TYPE

NUMBER

74HC112D;

74HCT112D

74HC112DB;

74HCT112DB

74HC112N;

74HCT112N

74HC112PW;

74HCT112PW

PACKAGE

NAME

SO16

SSOP16

DIP16

TSSOP16

DESCRIPTION

plastic small outline package; 16 leads; body width 3.9 mm

74HC/HCT112

VERSION

SOT109-1

SOT338-1

SOT38-1

SOT403-1

plastic shrink small outline package; 16 leads; body width 5.3 mm

plastic dual in-line package; 16 leads (300 mil); long body

plastic thin shrink small outline package; 16 leads; body width 4.4 mm

PIN DESCRIPTION

PIN NO.

1, 13

2, 12

3, 11

4, 10

5, 9

6, 7

15, 14

SYMBOL

1CP, 2CP

1K, 2K

1J, 2J

, 2S

1Q, 2Q

GND

, 2R

NAME AND FUNCTION

clock input (HIGH-to-LOW, edge triggered)

data inputs; ﬂip-ﬂops 1 and 2

set inputs (active LOW)

true ﬂip-ﬂop outputs

complement ﬂip-ﬂop outputs

ground (0 V)

reset inputs (active LOW)

positive supply voltage

Fig.1 Pin configuration.

Fig.2 Logic symbol.

Fig.3 IEC logic symbol.

1998 Jun 10

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with set and reset;

negative-edge trigger

FUNCTION TABLE

INPUTS

OPERATING MODE

asynchronous set

asynchronous reset

undetermined

toggle

load “0” (reset)

load “1” (set)

hold “no change”

Note

nCP

↓

74HC/HCT112

OUTPUTS

Fig.4 Functional diagram.

1. If nS

and nR

simultaneously go from LOW to HIGH, the output states will

be unpredictable.

H = HIGH voltage level

h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP

transition

L = LOW voltage level

l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP

transition

q = lower case letters indicate the state of the referenced output one set-up

time prior to the HIGH-to-LOW CP transition

X = don’t care

↓

= HIGH-to-LOW CP transition

Fig.5 Logic diagram (one flip-flop).

1998 Jun 10

Philips Semiconductors

Product speciﬁcation

Dual JK ﬂip-ﬂop with set and reset;

negative-edge trigger

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”.

Output capability: standard

category: flip-flops

74HC/HCT112

1998 Jun 10

参数对比

与74HCT112N相近的元器件有：74HC112、74HC112DB、74HC112N、74HC112PW、74HCT112DB、74HCT112、74HCT112D、74HCT112PW。描述及对比如下：

型号	74HCT112N	74HC112	74HC112DB	74HC112N	74HC112PW	74HCT112DB	74HCT112	74HCT112D	74HCT112PW
描述	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	8-Line To 3-Line Priority Encoders 16-SO -40 to 85	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16	HC/UH SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16
是否Rohs认证	符合	-	符合	符合	符合	符合	-	符合	符合
厂商名称	Philips Semiconductors (NXP Semiconductors N.V.)	-	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)	-	Philips Semiconductors (NXP Semiconductors N.V.)	Philips Semiconductors (NXP Semiconductors N.V.)
包装说明	DIP, DIP16,.3	-	SSOP, SSOP16,.3	DIP, DIP16,.3	TSSOP, TSSOP16,.25	SSOP, SSOP16,.3	-	SOP, SOP16,.25	TSSOP, TSSOP16,.25
Reach Compliance Code	unknow	-	unknow	unknow	unknow	unknow	-	unknow	unknow
JESD-30 代码	R-PDIP-T16	-	R-PDSO-G16	R-PDIP-T16	R-PDSO-G16	R-PDSO-G16	-	R-PDSO-G16	R-PDSO-G16
负载电容（CL）	50 pF	-	50 pF	50 pF	50 pF	50 pF	-	50 pF	50 pF
逻辑集成电路类型	J-K FLIP-FLOP	-	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	-	J-K FLIP-FLOP	J-K FLIP-FLOP
最大频率@ Nom-Su	20000000 Hz	-	20000000 Hz	20000000 Hz	20000000 Hz	20000000 Hz	-	20000000 Hz	20000000 Hz
最大I（ol）	0.004 A	-	0.004 A	0.004 A	0.004 A	0.004 A	-	0.004 A	0.004 A
功能数量	2	2	2	2	2	2	-	2	2
端子数量	16	16	16	16	16	16	-	16	16
最高工作温度	85 °C	-	125 °C	125 °C	125 °C	85 °C	-	85 °C	85 °C
最低工作温度	-40 °C	-	-40 °C	-40 °C	-40 °C	-40 °C	-	-40 °C	-40 °C
封装主体材料	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	DIP	-	SSOP	DIP	TSSOP	SSOP	-	SOP	TSSOP
封装等效代码	DIP16,.3	-	SSOP16,.3	DIP16,.3	TSSOP16,.25	SSOP16,.3	-	SOP16,.25	TSSOP16,.25
封装形状	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-	RECTANGULAR	RECTANGULAR
封装形式	IN-LINE	-	SMALL OUTLINE, SHRINK PITCH	IN-LINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH	SMALL OUTLINE, SHRINK PITCH	-	SMALL OUTLINE	SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源	5 V	-	2/6 V	2/6 V	2/6 V	5 V	-	5 V	5 V
认证状态	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	-	Not Qualified	Not Qualified
表面贴装	NO	YES	YES	NO	YES	YES	-	YES	YES
技术	CMOS	-	CMOS	CMOS	CMOS	CMOS	-	CMOS	CMOS
温度等级	INDUSTRIAL	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	AUTOMOTIVE	INDUSTRIAL	-	INDUSTRIAL	INDUSTRIAL
端子形式	THROUGH-HOLE	GULL WING	GULL WING	THROUGH-HOLE	GULL WING	GULL WING	-	GULL WING	GULL WING
端子节距	2.54 mm	-	0.635 mm	2.54 mm	0.635 mm	0.635 mm	-	1.27 mm	0.635 mm
端子位置	DUAL	DUAL	DUAL	DUAL	DUAL	DUAL	-	DUAL	DUAL
触发器类型	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	NEGATIVE EDGE	-	NEGATIVE EDGE	NEGATIVE EDGE