6-output 3.3V PCIe Clock Generator
9FGL06
DATASHEET
Description
The 9FGL06 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 6 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL06
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL06P1 can be programmed with a
user-defined power up default SMBus configuration.
Features/Benefits
•
Direct connection to 100 (xx41) or 85 (xx51)
•
•
transmission lines; saves 24 resistors compared to
standard PCIe devices
172mW typical power consumption (@3.3V); eliminates
thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
•
control input polarity
•
control input pull up/downs
•
slew rate for each output
•
differential output amplitude
•
33, 85 or 100Ω output impedance for each output
•
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
SMBus power up default; allows exact optimization to
customer requirements
8MHz - 40MHz input frequency with 9FGL08P1 device
(25MHz default); flexibility
OE# pins; support DIF power management
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•
6 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
•
9FGL0641 default Z
OUT
= 100
•
9FGL0651 default Z
OUT
= 85
•
9FGL06P1 factory programmable defaults
•
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
•
support
Easy AC-coupling to other logic families, see IDT
application note
AN-891
•
•
•
•
•
•
•
•
Key Specifications
•
•
•
•
•
•
•
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,
SSC is On
±100ppm frequency accuracy on all clocks
Block Diagram
vOE(5:0)#
XIN/CLKIN_25
6
REF
DIF5
603-25-150JA4I 25MHz
X2
SSC Capable
PLL
DIF4
DIF3
DIF2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
DIF1
DIF0
Note:
Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL06 DECEMBER 1, 2016
1
©2016 Integrated Device Technology, Inc.
9FGL06 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSS_EN_tri
1
X1_25
2
X2
3
VDDXTAL3.3
4
VDDREF3.3
5
vSADR/REF3.3
6
NC
7
GNDDIG
8
SCLK_3.3
9
SDATA_3.3
10
11 12 13 14 15 16 17 18 19 20
VDDDIG3.3
vOE0#
DIF0
DIF0#
DIF1
VDD3.3
VDDIO
VDDIO
DIF1#
NC
30
vOE3#
29
DIF3#
28
DIF3
27
VDDIO
9FGL06xx
epad is GND
VDD3.3
26
VDDA3.3
25
NC
24
vOE2#
23
DIF2#
22
DIF2
21
vOE1#
VDDIO
40-pin VFQFPN, 5x5 mm, 0.4mm pitch
v
^
prefix indicates internal 120KOhm pull down resistor
prefix indicates internal 120KOhm pull up resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
3
SMBus
DIFx
REF
OEx# Pin
True O/P
Comp. O/P
OE bit
0
X
X
Low
1
Hi-Z
2
Low
1
1
1
0
Running
Running
Running
1
1
1
1
1
Running
Disabled
Disabled
1
1
1
0
X
Disabled
Disabled Disabled
4
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running.
CKPWRGD_PD#
3. Input polarities defined at default values for 9FGL0641/0651.
4. See SMBus description for Byte 3, bit 4
Power Connections
Pin Number
VDD
4
5
11
12,17,27,32,39
26
VDDIO
GND
41
41
8
41
41
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
2
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
DECEMBER 1, 2016
9FGL06 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
vSS_EN_tri
X1_25
X2
VDDXTAL3.3
VDDREF3.3
vSADR/REF3.3
NC
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG3.3
VDDIO
vOE0#
DIF0
DIF0#
VDD3.3
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
NC
VDDA3.3
VDDIO
DIF3
DIF3#
vOE3#
VDD3.3
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
ePAD
PIN TYPE
LATCHED
IN
IN
OUT
PWR
PWR
LATCHED
I/O
N/A
GND
IN
I/O
PWR
PWR
IN
OUT
OUT
PWR
PWR
OUT
OUT
N/A
IN
OUT
OUT
IN
N/A
PWR
PWR
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
PWR
IN
GND
DESCRIPTION
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
Crystal input, Nominally 25.00MHz.
Crystal output.
Power supply for XTAL, nominal 3.3V
VDD for REF output. nominal 3.3V.
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
No Connection.
Ground pin for digital circuitry
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
3.3V digital power (dirty power)
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Power supply, nominal 3.3V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
No Connection.
3.3V power for the PLL core.
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply, nominal 3.3V
Power supply for differential outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
Connect paddle to ground.
DECEMBER 1, 2016
3
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
9FGL06 DATASHEET
Test Loads
Low-Power Differential Output Test Load
Terminations
Device
9FGL0641
9FGL0651
9FGL06P1
9FGL0641
9FGL0651
9FGL06P1
Zo (Ω)
100
100
100
85
85
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs”
for details.
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
4
DECEMBER 1, 2016
9FGL06 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL06. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
3.3V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to VDD, VDDA and VDDIO, if present.
MIN
-0.5
-0.5
TYP
MAX
3.9
V
DD
+ 0.5V
3.9
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
SMBus clock and data pins
-65
Human Body Model
2500
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.5V.
Electrical Characteristics–SMBus Parameters
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
SYMBOL
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
SMB
CONDITIONS
V
DDSMB
= 3.3V
V
DDSMB
= 3.3V
@ I
PULLUP
@ V
OL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus operating frequency
MIN
TYP
MAX
0.8
3.6
0.4
3.6
1000
300
500
UNITS NOTES
V
V
V
mA
V
ns
ns
kHz
2.1
4
2.7
1
1
2
Guaranteed by design and characterization, not 100% tested in production.
2.
The device must be powered up for the SMBus to function.
DECEMBER 1, 2016
5
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
