Blackfin
Embedded Processor
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
FEATURES
Up to 600 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations. See
Specifications on Page 28
Programmable on-chip voltage regulator (ADSP-BF523/
ADSP-BF525/ADSP-BF527 processors only)
Qualified for Automotive Applications. See
Automotive
Products on Page 87
289-ball and 208-ball CSP_BGA packages
PERIPHERALS
USB 2.0 high speed on-the-go (OTG) with integrated PHY
IEEE 802.3-compliant 10/100 Ethernet MAC
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
Host DMA port (HOSTDP)
2 dual-channel, full-duplex synchronous serial ports
(SPORTs), supporting eight stereo I
2
S channels
12 peripheral DMAs, 2 mastered by the Ethernet MAC
2 memory-to-memory DMAs with external request lines
Event handler with 54 interrupt inputs
Serial peripheral interface (SPI) compatible port
2 UARTs with IrDA support
2-wire interface (TWI) controller
Eight 32-bit timers/counters with PWM support
32-bit up/down counter with rotary support
Real-time clock (RTC) and watchdog timer
32-bit core timer
48 general-purpose I/Os (GPIOs), with programmable
hysteresis
NAND flash controller (NFC)
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
132K bytes of on-chip memory (See
Table 1 on Page 3
for L1
and L3 memory size details)
External memory controller with glueless support for SDRAM
and asynchronous 8-bit and 16-bit memories
Flexible booting options from external flash, SPI, and TWI
memory or from host devices including SPI, TWI, and UART
Code security with Lockbox Secure Technology
one-time-programmable (OTP) memory
Memory management unit providing memory protection
WATCHDOG TIMER
VOLTAGE REGULATOR*
JTAG TEST AND EMULATION
OTP MEMORY
RTC
PERIPHERAL
ACCESS BUS
COUNTER
SPORT0
SPORT1
B
L1 INSTRUCTION
MEMORY
EAB
USB
16
L1 DATA
MEMORY
INTERRUPT
CONTROLLER
UART1
UART0
GPIO
PORT F
DMA
CONTROLLER
DCB
DEB
NFC
DMA
ACCESS
BUS
PPI
SPI
TIMER7-1
TIMER0
BOOT
ROM
GPIO
PORT G
GPIO
PORT H
EXTERNAL PORT
FLASH, SDRAM CONTROL
EMAC
HOST DMA
*REGULATOR ONLY AVAILABLE ON ADSP-BF523/ADSP-BF525/ADSP-BF527 PROCESSORS
TWI
PORT J
Figure 1. Processor Block Diagram
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Rev. D
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ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
TABLE OF CONTENTS
Features ................................................................. 1
Memory ................................................................ 1
Peripherals ............................................................. 1
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Processor Peripherals ............................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 9
Host DMA Port .................................................... 9
Real-Time Clock ................................................... 9
Watchdog Timer ................................................ 10
Timers ............................................................. 10
Up/Down Counter and Thumbwheel Interface .......... 10
Serial Ports ........................................................ 10
Serial Peripheral Interface (SPI) Port ....................... 11
UART Ports ...................................................... 11
TWI Controller Interface ...................................... 12
10/100 Ethernet MAC .......................................... 12
Ports ................................................................ 12
Parallel Peripheral Interface (PPI) ........................... 13
USB On-The-Go Dual-Role Device Controller ........... 14
Code Security with Lockbox Secure Technology ......... 14
Dynamic Power Management ................................ 14
ADSP-BF523/ADSP-BF525/ADSP-BF527
Voltage Regulation ........................................... 16
ADSP-BF522/ADSP-BF524/ADSP-BF526
Voltage Regulation ........................................... 16
Clock Signals ...................................................... 16
Booting Modes ................................................... 18
Instruction Set Description .................................... 20
Development Tools .............................................. 20
Additional Information ........................................ 21
Related Signal Chains ........................................... 22
Lockbox Secure Technology Disclaimer .................... 22
Signal Descriptions ................................................. 23
Specifications ........................................................ 28
Operating Conditions
for ADSP-BF522/ADSP-BF524/ADSP-BF526
Processors ...................................................... 28
Operating Conditions for ADSP-BF523/ADSP-BF525/
ADSP-BF527 Processors .................................... 30
Electrical Characteristics ....................................... 32
Absolute Maximum Ratings ................................... 37
Package Information ............................................ 38
ESD Sensitivity ................................................... 38
Timing Specifications ........................................... 39
Output Drive Currents ......................................... 73
Test Conditions .................................................. 75
Environmental Conditions .................................... 79
289-Ball CSP_BGA Ball Assignment ........................... 80
208-Ball CSP_BGA Ball Assignment ........................... 83
Outline Dimensions ................................................ 86
Surface-Mount Design .......................................... 87
Automotive Products .............................................. 87
Ordering Guide ..................................................... 88
REVISION HISTORY
7/13—Rev. C to Rev. D
Updated
Development Tools .................................... 20
Corrected footnote 9 and added footnote 11 in
Operating Conditions for ADSP-BF523/ADSP-BF525/
ADSP-BF527 Processors .......................................... 30
Rev. D | Page 2 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
GENERAL DESCRIPTION
The ADSP-BF52x processors are members of the Blackfin fam-
ily of products, incorporating the Analog Devices/Intel Micro
Signal Architecture (MSA). Blackfin
®
processors combine a
dual-MAC state-of-the-art signal processing engine, the advan-
tages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
The ADSP-BF52x processors are completely code compatible
with other Blackfin processors. The ADSP-BF523/
ADSP-BF525/ADSP-BF527 processors offer performance up to
600 MHz. The ADSP-BF522/ADSP-BF524/ADSP-BF526 pro-
cessors offer performance up to 400 MHz and reduced static
power consumption. Differences with respect to peripheral
combinations are shown in
Table 1.
Table 1. Processor Comparison
ADSP-BF522
ADSP-BF524
ADSP-BF526
ADSP-BF523
ADSP-BF525
ADSP-BF527
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like program-
mability, multimedia support, and leading-edge signal
processing in one integrated package.
PORTABLE LOW POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. They are produced with a low power and low
voltage design methodology and feature on-chip dynamic
power management, which is the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. This capability can result in a substantial reduc-
tion in power consumption, compared with just varying the
frequency of operation. This allows longer battery life for
portable appliances.
SYSTEM INTEGRATION
The ADSP-BF52x processors are highly integrated system-on-a-
chip solutions for the next generation of embedded network
connected applications. By combining industry-standard inter-
faces with a high performance signal processing core, cost-
effective applications can be developed quickly, without the
need for costly external components. The system peripherals
include an IEEE-compliant 802.3 10/100 Ethernet MAC, a USB
2.0 high speed OTG controller, a TWI controller, a NAND flash
controller, two UART ports, an SPI port, two serial ports
(SPORTs), eight general purpose 32-bit timers with PWM capa-
bility, a core timer, a real-time clock, a watchdog timer, a Host
DMA (HOSTDP) interface, and a parallel peripheral interface
(PPI).
Feature
Host DMA
USB
Ethernet MAC
Internal Voltage Regulator
TWI
SPORTs
UARTs
SPI
GP Timers
GP Counter
Watchdog Timers
RTC
Parallel Peripheral Interface
GPIOs
L1 Instruction SRAM
L1 Instruction SRAM/Cache
L1 Data SRAM
L1 Data SRAM/Cache
L1 Scratchpad
L3 Boot ROM
Maximum Instruction Rate
1
Maximum System Clock Speed
Package Options
Memory (bytes)
1
1
1
1
1
1
1
–
1
1
–
1
1
–
–
1
–
–
1
–
–
–
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
8
8
8
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
48 48 48 48 48 48
48K 48K 48K 48K 48K 48K
16K 16K 16K 16K 16K 16K
32K 32K 32K 32K 32K 32K
32K 32K 32K 32K 32K 32K
4K 4K 4K 4K 4K 4K
32K 32K 32K 32K 32K 32K
400 MHz
600 MHz
100 MHz
133 MHz
289-Ball CSP_BGA
208-Ball CSP_BGA
PROCESSOR PERIPHERALS
The ADSP-BF52x processors contain a rich set of peripherals
connected to the core via several high bandwidth buses, provid-
ing flexibility in system configuration as well as excellent overall
system performance (see the block diagram
on Page 1).
These Blackfin processors contain dedicated network commu-
nication modules and high speed serial and parallel ports, an
interrupt controller for flexible management of interrupts from
the on-chip peripherals or external sources, and power manage-
ment control functions to tailor the performance and power
characteristics of the processor and system to many application
scenarios.
All of the peripherals, except for the general-purpose I/O, TWI,
real-time clock, and timers, are supported by a flexible DMA
structure. There are also separate memory DMA channels dedi-
cated to data transfers between the processor's various memory
spaces, including external SDRAM and asynchronous memory.
Multiple on-chip buses running at up to 133 MHz provide
enough bandwidth to keep the processor core running along
with activity on all of the on-chip and external peripherals.
The ADSP-BF523/ADSP-BF525/ADSP-BF527 processors
include an on-chip voltage regulator in support of the proces-
sor’s dynamic power management capability. The voltage
Maximum instruction rate is not available with every possible SCLK selection.
Rev. D | Page 3 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
regulator provides a range of core voltage levels when supplied
from V
DDEXT
. The voltage regulator can be bypassed at the user's
discretion.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation
are supported.
BLACKFIN PROCESSOR CORE
As shown in
Figure 2,
the Blackfin processor core contains two
16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs,
four video ALUs, and a 40-bit shifter. The computation units
process 8-, 16-, or 32-bit data from the register file.
ADDRESS ARITHMETIC UNIT
I3
I2
I1
I0
DA1
DA0
TO MEMORY
32
32
L3
L2
L1
L0
B3
B2
B1
B0
M3
M2
M1
M0
DAG1
DAG0
SP
FP
P5
P4
P3
P2
P1
P0
32
RAB
32
PREG
SD
LD1
LD0
32
32
32
R7.H
R6.H
R5.H
R4.H
R3.H
R2.H
R1.H
R0.H
R7.L
R6.L
R5.L
R4.L
R3.L
R2.L
R1.L
R0.L
32
32
ASTAT
SEQUENCER
16
8
8
8
16
ALIGN
8
DECODE
BARREL
SHIFTER
40
A0
32
40
40
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and pop-
ulation count, modulo 2
32
multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations,
16-bit and 8-bit adds with clipping, 8-bit average operations,
and 8-bit subtract/absolute value/accumulate (SAA) operations.
Also provided are the compare/select and vector search
instructions.
For certain instructions, two 16-bit ALU operations can be per-
formed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). If the second ALU is used,
quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execu-
tion, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-over-
head looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simulta-
neous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
Rev. D | Page 4 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory manage-
ment unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instruc-
tions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruc-
tion can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
The Blackfin processor assembly language uses an algebraic syn-
tax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
0xFFFF FFFF
CORE MMR REGISTERS (2M BYTES)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTES)
0xFFC0 0000
RESERVED
0xFFB0 1000
SCRATCHPAD SRAM (4K BYTES)
0xFFB0 0000
RESERVED
0xFFA1 4000
INSTRUCTION SRAM / CACHE (16K BYTES)
0xFFA1 0000
0xFFA0 C000
INSTRUCTION BANK B SRAM (16K BYTES)
0xFFA0 8000
INSTRUCTION BANK A SRAM (32K BYTES)
0xFFA0 0000
RESERVED
0xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTES)
0xFF90 4000
DATA BANK B SRAM (16K BYTES)
0xFF90 0000
RESERVED
0xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTES)
0xFF80 4000
DATA BANK A SRAM (16K BYTES)
0xFF80 0000
RESERVED
0xEF00 8000
BOOT ROM (32K BYTES)
RESERVED
0x2040 0000
ASYNC MEMORY BANK 3 (1M BYTES)
0x2030 0000
ASYNC MEMORY BANK 2 (1M BYTES)
0x2020 0000
ASYNC MEMORY BANK 1 (1M BYTES)
0x2010 0000
ASYNC MEMORY BANK 0 (1M BYTES)
0x2000 0000
RESERVED
0x08 00 0000
SDRAM MEMORY (16M BYTES
0x0000 0000
128M BYTES)
EXTERNAL MEMORY MAP
INTERNAL MEMORY MAP
RESERVED
0xEF00 0000
Figure 3. Internal/External Memory Map
Internal (On-Chip) Memory
The processor has three blocks of on-chip memory providing
high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
64K bytes SRAM, of which 16K bytes can be configured as a
four-way set-associative cache. This memory is accessed at full
processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of up to two banks of up to 32K bytes each. Each memory
bank is configurable, offering both cache and SRAM functional-
ity. This memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
MEMORY ARCHITECTURE
The Blackfin processor views memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. See
Figure 3.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip
memory system, accessed through the external bus interface
unit (EBIU), provides expansion with SDRAM, flash memory,
and SRAM, optionally accessing up to 132M bytes of
physical memory.
The memory DMA controller provides high-bandwidth data-
movement capability. It can perform block transfers of code
or data between the internal memory and the external
memory spaces.
External (Off-Chip) Memory
External memory is accessed via the EBIU. This 16-bit interface
provides a glueless connection to a bank of synchronous DRAM
(SDRAM), as well as up to four banks of asynchronous memory
devices including flash, EPROM, ROM, SRAM, and memory
mapped I/O devices.
Rev. D | Page 5 of 88 | July 2013
