BUK9610-100B
N-channel TrenchMOS logic level FET
Rev. 03 — 31 January 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product has been designed and qualified to
the appropriate AEC standard for use in automotive critical applications.
1.2 Features and benefits
AEC Q101 compliant
Low conduction losses due to low
on-state resistance
Suitable for logic level gate drive
sources
Suitable for thermally demanding
environments due to 175 °C rating
1.3 Applications
12 V, 24 V and 42 V loads
Automotive systems
General purpose power switching
Motors, lamps and solenoids
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
Quick reference data
Parameter
drain-source
voltage
drain current
total power
dissipation
drain-source
on-state resistance
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
V
GS
= 5 V; T
mb
= 25 °C;
see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
[1]
Min
-
-
-
Typ
-
-
-
Max Unit
100
75
300
V
A
W
Static characteristics
R
DSon
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 11;
see
Figure 12
-
-
8.3
8.6
9.7
10
mΩ
mΩ
Nexperia
BUK9610-100B
N-channel TrenchMOS logic level FET
Table 1.
Symbol
E
DS(AL)S
Quick reference data
…continued
Parameter
non-repetitive
drain-source
avalanche energy
gate-drain charge
Conditions
I
D
= 75 A; V
sup
≤
100 V;
R
GS
= 50
Ω;
V
GS
= 5 V;
T
j(init)
= 25 °C; unclamped
V
GS
= 5 V; I
D
= 25 A;
V
DS
= 80 V; T
j
= 25 °C;
see
Figure 13
Min
-
Typ
-
Max Unit
629
mJ
Avalanche ruggedness
Dynamic characteristics
Q
GD
-
32
-
nC
[1]
Continuous current is limited by package.
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT404 (D2PAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
BUK9610-100B
D2PAK
Description
Version
plastic single-ended surface-mounted package (D2PAK); 3 leads SOT404
(one lead cropped)
Type number
BUK9610-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 31 January 2011
2 of 14
Nexperia
BUK9610-100B
N-channel TrenchMOS logic level FET
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
T
mb
= 25 °C; V
GS
= 5 V; see
Figure 1;
see
Figure 3
T
mb
= 100 °C; V
GS
= 5 V; see
Figure 1
I
DM
P
tot
T
stg
T
j
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
source current
peak source current
non-repetitive drain-source
avalanche energy
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
I
D
= 75 A; V
sup
≤
100 V; R
GS
= 50
Ω;
V
GS
= 5 V; T
j(init)
= 25 °C; unclamped
[1]
[2]
[1]
[2]
[2]
In accordance with the Absolute Maximum Rating System (IEC 60134).
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
R
GS
= 20 kΩ
Min
-
-
-15
-
-
-
-
-
-55
-55
-
-
-
-
Max
100
100
15
110
75
75
438
300
175
175
110
75
438
629
Unit
V
V
V
A
A
A
A
W
°C
°C
A
A
A
mJ
T
mb
= 25 °C; pulsed; t
p
≤
10 µs;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
Source-drain diode
Avalanche ruggedness
[1]
[2]
Current is limited by power dissipation chip rating.
Continuous current is limited by package.
120
I
D
(A)
03ng70
120
P
der
(%)
80
03na19
Capped at 75 A due to package
80
40
40
0
0
50
100
150
T
mb
(°C)
200
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
©
BUK9610-100B
All information provided in this document is subject to legal disclaimers.
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 31 January 2011
3 of 14
Nexperia
BUK9610-100B
N-channel TrenchMOS logic level FET
10
3
I
D
(A)
10
2
Limit R
DSon
= V
DS
/I
D
02ng68
t
p
= 10
µs
100
µs
1 ms
DC
Capped at 75 A due to package
10
10 ms
100 ms
1
1
10
10
2
V
DS
(V)
10
3
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
BUK9610-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 31 January 2011
4 of 14
Nexperia
BUK9610-100B
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction
to mounting base
thermal resistance from junction
to ambient
Conditions
see
Figure 4
mounted on a printed-circuit
board ; minimum footprint
Min
-
-
Typ
-
50
Max
0.5
-
Unit
K/W
K/W
1
Z
th(j-mb)
(K/W)
10
−1
03ng69
δ
= 0.5
0.2
0.1
0.05
10
−2
0.02
P
δ
=
t
p
T
Single Shot
10
−3
10
−6
t
p
T
t
10
−5
10
−4
10
−3
10
−2
10
−1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
BUK9610-100B
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 03 — 31 January 2011
5 of 14
