16.1 Units of Measure ............................................... 94
17. Revision History ....................................................... 95
18. Sales, Solutions, and Legal Information ................ 98
Document Number: 001-55036 Rev. *G
Page 2 of 98
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PRELIMINARY
PSoC
®
5: CY8C54 Family Datasheet
1. Architectural Overview
Introducing the CY8C54 family of ultra low power, flash Programmable System-on-Chip (PSoC) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C54 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Digital Interconnect
GPIOs
Usage Example for UDB
Sequencer
4 to 33 MHz
(Optional
)
SYSTEM WIDE
RESOURCES
Xtal
Osc
Digital System
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
Quadrature Decoder
UDB
16- Bit
PWM
UDB
16- Bit PRS
UDB
UDB
UDB
CAN
2.0
I2C
Master
/
Slave
SIO
22
UDB
UDB
Clock Tree
UDB
I 2C Slave
UDB
UDB
8- Bit SPI
UDB
12- Bit SPI
UDB
8- Bit
Timer
Logic
UDB
GPIOs
UDB
UDB
UDB
UDB
IMO
4x
Timer
Counter
PWM
FS USB
2.0
USB
PHY
32.768 KHz
( Optional
)
Logic
UDB
UART
UDB
UDB
12- Bit PWM
UDB
UDB
UDB
RTC
Timer
System Bus
WDT
and
Wake
GPIOs
Memory System
EEPROM
SRAM
CPU System
8051 or
Cortex M3 CPU
Interrupt
Controller
Program &
Debug
Program
Debug &
Trace
EMIF
ILO
Clocking System
Power Management
System
FLASH
Cache
Controller
PHUB
DMA
Boundary
Scan
SIOs
LCD Direct
Drive
Digital
Filter
Block
Analog System
ADCs
2x
SAR
ADC
+
4x
Opamp
-
POR and
LVD
Sleep
Power
1.71 to
5.5 V
1.8V LDO
SMP
4 x SC/ CT Blocks
( TIA, PGA, Mixer etc
)
Temperature
Sensor
CapSense
3 per
Opamp
4 x DAC
4x
CMP
-
0. 5 to 5.5 V
( Optional
)
Figure 1-1
illustrates the major components of the CY8C54
family. They are:
ARM Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, low
power UDBs. PSoC Creator provides a library of pre-built and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. The designer can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
Page 3 of 98
Document Number: 001-55036 Rev. *G
GPIOs
+
GPIOs
GPIOs
GPIOs
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PRELIMINARY
PSoC
®
5: CY8C54 Family Datasheet
CY8C54 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I
2
C slave, master, and multi-master;
FS USB; and Full CAN 2.0b.
For more details on the peripherals see the
“Example
Peripherals”
section on page 32 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem”
section on page 32 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 0.1% error
over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Analog mixers
Voltage references
ADCs
DACs
DFB
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined ARM Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. The designer can enable
an ECC for high reliability applications. A powerful and flexible
protection model secures the user's sensitive information,
allowing selective memory block locking for read and write
protection. Two KB of byte-writable EEPROM is available
on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after power on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the V
DDIO
pins. Every GPIO
has analog I/O, LCD drive, flexible interrupt generation, slew rate
control, and digital I/O capability. The SIOs on PSoC allow V
OH
to be set independently of V
DDIO
when used as outputs. When
SIOs are in input mode they are high impedance. This is true
even when the device is not powered or when the pin voltage
goes above the supply voltage. This makes the SIO ideally suited
for use on an I
2
C bus where the PSoC may not be powered when
other devices on the bus are. The SIO pins also have high
current sink capability for applications such as LED drives. The
programmable input threshold feature of the SIO can be used to
make the SIO function as a general purpose analog comparator.
For devices with FS USB the USB physical interface is also
provided (USBIO). When not using USB these pins may also be
used for limited digital functionality and device programming. All
the features of the PSoC I/Os are covered in detail in the
“I/O
System and Routing”
section on page 26 of this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the master clock base for
the system, and has 1% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low power Internal Low Speed Oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in RTC applications. The clocks, together
with programmable clock dividers, provide the flexibility to
integrate most timing requirements.
The CY8C54 family supports a wide supply operating range from
1.71 to 5.5 V. This allows operation from regulated supplies such
as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly
Page 4 of 98
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
The CY8C54 family offers two successive approximation
register (SAR) ADCs. Featuring 12-bit conversions at up to 1 M
samples per second, they also offer low nonlinearity and offset
errors and SNR better than 70 dB. They are well suited for a
variety of higher speed analog applications.
The output of either ADC can optionally feed the programmable
DFB via DMA without CPU intervention. The designer can
configure the DFB to perform IIR and FIR digital filters and
several user defined custom functions. The DFB can implement
filters with up to 64 taps. It can perform a 48-bit
multiply-accumulate (MAC) operation in one clock cycle.
Four high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
DAC outputs using the UDB array. This can be used to create a
pulse width modulated (PWM) DAC of up to 10 bits, at up to
48 kHz. The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADCs, DACs, and DFB, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the
“Analog Subsystem”
section on page 44 of this
datasheet for more details.
Document Number: 001-55036 Rev. *G
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5: CY8C54 Family Datasheet
from a wide range of battery types. In addition, it provides an
integrated high efficiency synchronous boost converter that can
power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery
or solar cell. In addition, the designer can use the boost converter
to generate other voltages required by the device, such as a
3.3 V supply for LCD glass drive. The boost’s output is available
on the V
BOOST
pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low power modes. These include
a 300 nA hibernate mode with RAM retention and a 2 µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 2 mA when the CPU is running at
6 MHz.
The details of the PSoC power modes are covered in the
“Power
System”
section on page 22 of this datasheet.
PSoC uses JTAG (4 wire) or SWD (2 wire) interfaces for
programming, debug, and test. Using these standard interfaces
enables the designer to debug or program the PSoC with a
variety of hardware solutions from Cypress or third party
vendors. The Cortex-M3 debug and trace modules include Flash
Patch and Breakpoint (FPB), Data Watchpoint and Trace (DWT),
Embedded Trace Macrocell (ETM), and Instrumentation Trace
Macrocell (ITM). These modules have many features to help
solve difficult debug and trace problems. Details of the
programming, test, and debugging interfaces are discussed in
the
“Programming, Debug Interfaces, Resources”
section on
page 53 of this datasheet.
2. Pinouts
The Vddio pin that supplies a particular set of pins is indicated
by the black lines drawn on the pinout diagrams in
Figure 2-2
and
Figure 2-3.
Using the Vddio pins, a single PSoC can support
multiple interface voltage levels, eliminating the need for off-chip
level shifters. Each Vddio may sink up to 100 mA total to its
associated I/O pins and opamps. On the 68 pin and 100 pin
devices each set of Vddio associated pins may sink up to
100 mA. The 48 pin device may sink up to 100 mA total for all
Vddio0 plus Vddio2 associated I/O pins and 100 mA total for all
Vddio1 plus Vddio3 associated I/O pins.
[3]
Figure 2-1. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(OpAmp2out, GPIO) P0[0]
(OpAmp0out, GPIO) P0[1]
(OpAmp0+, GPIO) P0[2]
(OpAmp0-/Extref0, GPIO) P0[3]
Vddio0
(OpAmp2+, GPIO) P0[4]
(OpAmp2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
Vccd
Vssd
Vddd
(TRACECLK, GPIO) P2[3]
(TRACEDATA[0], GPIO) P2[4]
Vddio2
(TRACEDATA[1], GPIO) P2[5]
(TRACEDATA[2], GPIO) P2[6]
(TRACEDATA[3], GPIO) P2[7]
Vssb
Ind
Vboost
Vbat
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Lines show
Vddio to I/O
supply
association
SSOP
Vdda
Vssa
Vcca
P15[3] (GPIO, kHz XTAL: Xi)
P15[2] (GPIO, kHz XTAL: Xo)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
Vddio3
P15[1] (GPIO, MHz XTAL: Xi)
P15[0] (GPIO, MHz XTAL: Xo)
Vccd
Vssd
Vddd
[3]
P15[7] (USBIO, D-, SWDCK)
[3]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
Vddio1
P1[5] (GPIO, nTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, configurable XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
Note
3. Pins are No Connect (NC) on devices without USB. NC means that the pin has no electrical connection. The pin can be left floating or tied to a supply voltage or ground.
