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HUF75652G3

MOSFET 75a 100VN-Ch MOSFET

器件类别:分立半导体    晶体管   

厂商名称:ON Semiconductor(安森美)

厂商官网:http://www.onsemi.cn

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器件参数
参数名称
属性值
Brand Name
ON Semiconductor
是否无铅
不含铅
制造商包装代码
340CK
Reach Compliance Code
not_compliant
ECCN代码
EAR99
Factory Lead Time
10 weeks
外壳连接
DRAIN
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
100 V
最大漏极电流 (Abs) (ID)
75 A
最大漏极电流 (ID)
75 A
最大漏源导通电阻
0.008 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码
TO-247
JESD-30 代码
R-PSFM-T3
JESD-609代码
e3
元件数量
1
端子数量
3
工作模式
ENHANCEMENT MODE
最高工作温度
175 °C
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
FLANGE MOUNT
峰值回流温度(摄氏度)
NOT SPECIFIED
极性/信道类型
N-CHANNEL
最大功率耗散 (Abs)
515 W
认证状态
Not Qualified
表面贴装
NO
端子面层
Tin (Sn)
端子形式
THROUGH-HOLE
端子位置
SINGLE
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
Base Number Matches
1
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HUF75652G3
Data Sheet
October
2013
N-Channel UltraFET Power MOSFET
100 V, 75 A, 8 mΩ
Packaging
JEDEC TO-247
SOURCE
DRAIN
GATE
Features
• Ultra Low On-Resistance
- r
DS(ON)
= 0.008Ω,
V
GS
=
10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
• Peak Current vs Pulse Width Curve
DRAIN
(TAB)
HUF75652G3
• UIS Rating Curve
Symbol
D
Ordering Information
PART NUMBER
HUF75652G3
G
PACKAGE
TO-247
BRAND
75652G
S
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
HUF75652G3
UNITS
V
V
V
A
A
100
100
±20
75
75
Figure 4
Figure 6
515
3.44
-55 to 175
300
260
W
W/
o
C
o
C
o
C
o
C
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DSS
Drain to Gate Voltage (R
GS
= 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
Drain Current
Continuous (T
C
= 25
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Continuous (T
C
= 100
o
C, V
GS
= 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
Derate Above 25
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J
, T
STG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
NOTES:
1. T
J
= 25
o
C to 150
o
C.
CAUTION:
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
HUF75652G3 Rev.
C0
HUF75652G3
Electrical Specifications
PARAMETER
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
BV
DSS
I
DSS
I
D
= 250µA, V
GS
= 0V (Figure 11)
V
DS
= 95V, V
GS
= 0V
V
DS
= 90V, V
GS
= 0V, T
C
= 150
o
C
Gate to Source Leakage Current
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
Drain to Source On Resistance
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
Thermal Resistance Junction to
Ambient
R
θJC
R
θJA
TO-247
-
-
-
-
0.29
30
o
C/W
o
C/W
T
C
= 25
o
C, Unless Otherwise Specified
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
100
-
-
-
-
-
-
-
-
1
250
±100
V
µA
µA
nA
I
GSS
V
GS
=
±20V
V
GS(TH)
r
DS(ON)
V
GS
= V
DS
, I
D
= 250µA (Figure 10)
I
D
= 75A, V
GS
= 10V (Figures 9)
2
-
-
0.0067
4
0.008
V
SWITCHING SPECIFICATIONS
(V
GS
= 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Gate Charge at 10V
Threshold Gate Charge
Gate to Source Gate Charge
Gate to Drain “Miller” Charge
CAPACITANCE SPECIFICATIONS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
C
ISS
C
OSS
C
RSS
V
DS
= 25V, V
GS
= 0V,
f = 1MHz
(Figure 12)
-
-
-
7585
2345
630
-
-
-
pF
pF
pF
Q
g(TOT)
Q
g(10)
Q
g(TH)
Q
gs
Q
gd
V
GS
= 0V to 20V
V
GS
= 0V to 10V
V
GS
= 0V to 2V
V
DD
= 50V,
I
D
= 75A,
I
g(REF)
= 1.0mA
(Figure 13)
-
-
-
-
-
393
211
14
26
74
475
255
16.5
-
-
nC
nC
nC
nC
nC
t
ON
t
d(ON)
t
r
t
d(OFF)
t
f
t
OFF
V
DD
= 50V, I
D
= 75A, V
GS
=
10V, R
GS
= 2.0Ω
-
-
-
-
-
-
-
18.5
195
80
190
-
320
-
-
-
-
410
ns
ns
ns
ns
ns
ns
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
SYMBOL
V
SD
I
SD
= 75A
I
SD
= 35A
Reverse Recovery Time
Reverse Recovered Charge
t
rr
Q
RR
I
SD
= 75A, dI
SD
/dt = 100A/µs
I
SD
= 75A, dI
SD
/dt = 100A/µs
TEST CONDITIONS
MIN
-
-
-
-
TYP
-
-
-
-
MAX
1.25
1.00
150
490
UNITS
V
V
ns
nC
©2001 Fairchild Semiconductor Corporation
HUF75652G3 Rev.
C0
HUF75652G3
Typical Performance Curves
1.2
POWER DISSIPATION MULTIPLIER
1.0
0.8
0.6
0.4
0.2
0
0
25
50
75
100
125
150
175
T
C
, CASE TEMPERATURE (
o
C)
0
25
50
75
100
125
150
T
C
, CASE TEMPERATURE (
o
C)
80
I
D
, DRAIN CURRENT (A)
60
V
GS
= 10V
40
20
175
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
1
THERMAL IMPEDANCE
Z
θJC
, NORMALIZED
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
P
DM
0.1
t
1
t
2
NOTES:
DUTY FACTOR: D = t
1
/t
2
PEAK T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-3
10
-2
t, RECTANGULAR PULSE DURATION (s)
10
-1
10
0
10
1
SINGLE PULSE
0.01
10
-5
10
-4
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000
T
C
= 25
o
C
FOR TEMPERATURES
ABOVE 25
o
C DERATE PEAK
CURRENT AS FOLLOWS:
I = I
25
175 - T
C
150
I
DM
, PEAK CURRENT (A)
1000
V
GS
= 10V
V
GS
= 20V
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10
-5
10
-4
10
-3
10
-2
t, PULSE WIDTH (s)
10
-1
10
0
10
1
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
HUF75652G3 Rev.
C0
HUF75652G3
Typical Performance Curves
1000
(Continued)
1000
I
AS
, AVALANCHE CURRENT (A)
If R = 0
t
AV
= (L)(I
AS
)/(1.3*RATED BV
DSS
- V
DD
)
If R
0
t
AV
= (L/R)ln[(I
AS
*R)/(1.3*RATED BV
DSS
- V
DD
) +1]
I
D
, DRAIN CURRENT (A)
100
100µs
100
STARTING T
J
= 25
o
C
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY r
DS(ON)
SINGLE PULSE
T
J
= MAX RATED
T
C
= 25
o
C
1
10
100
500
10ms
STARTING T
J
= 150
o
C
1
10
0.01
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
1
t
AV
, TIME IN AVALANCHE (ms)
0.1
10
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
200
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
V
DD
= 15V
I
D
, DRAIN CURRENT (A)
200
V
GS
= 20V
V
GS
= 10V
150
V
GS
= 7V
V
GS
= 6V
V
GS
=5V
I
D,
DRAIN CURRENT (A)
150
100
T
J
= 175
o
C
50
100
T
J
= 25
o
C
50
0
2
3
T
J
= -55
o
C
4
5
V
GS
, GATE TO SOURCE VOLTAGE (V)
6
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
T
C
= 25
o
C
0
1
2
3
V
DS
, DRAIN TO SOURCE VOLTAGE (V)
4
0
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
2.5
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2.0
NORMALIZED GATE
THRESHOLD VOLTAGE
1.2
V
GS
= V
DS
, I
D
= 250µA
1.0
1.5
0.8
1.0
V
GS
= 10V, I
D
= 75A
0.5
-80
-40
0
40
80
120
T
J
, JUNCTION TEMPERATURE (
o
C)
160
200
0.6
0.4
-80
-40
0
40
80
120
160
200
T
J
, JUNCTION TEMPERATURE (
o
C)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
©2001 Fairchild Semiconductor Corporation
HUF75652G3 Rev.
C0
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