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器件参数

参数名称

属性值

是否Rohs认证

符合

厂商名称

SK Hynix(海力士)

零件包装代码

BGA

包装说明

LFBGA, BGA144,12X12,32

针数

144

Reach Compliance Code

unknown

ECCN代码

EAR99

访问模式

FOUR BANK PAGE BURST

最长访问时间

0.28 ns

其他特性

AUTO/SELF REFRESH

最大时钟频率 (fCLK)

550 MHz

I/O 类型

COMMON

JESD-30 代码

S-PBGA-B144

长度

12 mm

内存密度

268435456 bit

内存集成电路类型

DDR DRAM

内存宽度

功能数量

端口数量

端子数量

144

字数

8388608 words

字数代码

8000000

工作模式

SYNCHRONOUS

最高工作温度

85 °C

最低工作温度

组织

8MX32

输出特性

3-STATE

封装主体材料

PLASTIC/EPOXY

封装代码

LFBGA

封装等效代码

BGA144,12X12,32

封装形状

SQUARE

封装形式

GRID ARRAY, LOW PROFILE, FINE PITCH

峰值回流温度（摄氏度）

260

电源

2 V

认证状态

Not Qualified

刷新周期

4096

座面最大高度

1.3 mm

自我刷新

YES

连续突发长度

最大待机电流

0.03 A

最大压摆率

1.05 mA

最大供电电压 (Vsup)

2.1 V

最小供电电压 (Vsup)

1.9 V

标称供电电压 (Vsup)

2 V

表面贴装

YES

技术

CMOS

温度等级

OTHER

端子形式

BALL

端子节距

0.8 mm

端子位置

BOTTOM

处于峰值回流温度下的最长时间

宽度

12 mm

文档预览

HY5RS573225F(P)

256M (8Mx32) GDDR3 SDRAM

HY5RS573225F(P)

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 1.1 / Sep. 2005

1HY5RS573225F(P)

Revision History

Revision No.

0.1

0.2

1.0

1.1

Supports Lead free parts

AC, DC Parameter Change

Driver Strength, IDD6, tDQSH/L, tCH/L change & tRCDW insert

Changed IDD Value (2P/ 3P)

History

Draft Date

Nov. 2004

Feb. 2005

Mar. 2005

Sep. 2005

Remark

Rev. 1.1 / Sep. 2005

1HY5RS573225F(P)

DESCRIPTION

The Hynix HY5RS573225 is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

The Hynix HY5RS573225 is internally configured as a quad-bank DRAM.

The Hynix HY5RS573225 uses a double data rate architecture to achieve high-speed opreration. The double date rate

architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock

cycle at the I/O pins. A single read or write access for the Hynix HY5RS573225 consists of a 4n-bit wide, every two-

clock-cycles data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data trans-

fers at the I/O pins. Read and write accesses to the Hynix HY5RS573225 is burst oriented; accesses start at a selected

locations and continue for a programmed number of locations in a programmed sequence. Accesses begin with the

registration of an ACTIVE command, which is then followed by a READ of WRITE command. The address bits regis-

tered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the

bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to

select the starting column location for the burst access. Prior to normal operation, the Hynix HY5RS573225 must be

initialized.

FEATURES

•

=2.0V

0.1V, V

DDQ

=2.0V

0.1V

Single ended READ Strobe (RDQS) per byte

Single ended WRITE Strobe (WDQS) per byte

Internal, pipelined double-data-rate (DDR) architec-

ture; two data accesses per clock cycle

Calibrated output drive

Differential clock inputs (CK and CK#)

Commands entered on each positive CK edge

RDQS edge-aligned with data for READs; with WDQS

center-aligned with data for WRITEs

Four internal banks for concurrent operation

•

Data mask (DM) for masking WRITE data

4n prefetch

Programmable burst lengths: 4

32ms, 4K-cycle auto refresh

Auto precharge option

Auto Refresh and Self Refresh Modes

1.8v Pseudo Open Drain I/O

Concurrent Auto Precharge support

tRAS lockout support, Active Termination support

Programmable Write latency(1,2 or 3)

ORDERING INFORMATION

Part No.

HY5RS573225F(P)-12

HY5RS573225F(P)-13

HY5RS573225F(P)-14

HY5RS573225F(P)-15

HY5RS573225F(P)-16

HY5RS573225F(P)-18

HY5RS573225F(P)-2

HY5RS573225F(P)-22

VDD=2.0V,

VDDQ=2.0V

Power Supply

Clock

Frequency

800MHz

750MHz

700MHz

650MHz

600MHz

550MHz

500MHz

450MHz

Max Data

Rate

1600Mbps/pin

1500Mbps/pin

1400Mbps/pin

1300Mbps/pin

1200Mbps/pin

1100Mbps/pin

1000Mbps/pin

900Mbps/pin

POD_18

12mmx12mm

144Ball FBGA

Interface

Package

Note) Hynix supports Lead free parts for each speed grade with same specification, except Lead free materials.

We'll add "P" character after "F" for Lead free product.

For example, the part number of 500MHz Lead free product is HY5RS573225FP-2.

Rev. 1.1 / Sep. 2005

1HY5RS573225F(P)

BALLOUT CONFIGURATION

WDQS0

RDQS0

VSSQ

DQ3

DQ2

DQ0

DQ31

DQ29

DQ28

VSSQ

RDQS3

WDQS3

DQ4

DM0

VDDQ

DQ1

VDDQ

DQ30

VDDQ

DM3

DQ27

DQ6

DQ5

VSSQ

VDD

VSSQ

DQ26

DQ25

DQ7

RFU3

VDD

VSS

VSSQ

VSS

VSSQ

VSS

VDD

RFU4

DQ24

DQ17

DQ16

VDDQ

VSSQ

VSS

therm

VSS

therm

VSS

therm

VSS

therm

VSSQ

VDDQ

DQ15

DQ14

DQ19

DQ18

VDDQ

VSSQ

VSS

therm

VSS

therm

VSS

therm

VSS

therm

VSSQ

VDDQ

DQ13

DQ12

WDQS2

RDQS2

VDDQ

VSSQ

VSS

therm

VSS

therm

VSS

therm

VSS

therm

VSSQ

VDDQ

RDQS1

WDQS1

DQ20

DM2

VDDQ

VSSQ

VSS

therm

VSS

therm

VSS

therm

VSS

therm

VSSQ

VDDQ

DM1

DQ11

DQ21

DQ22

VDDQ

VSSQ

VSS

VSSQ

VDDQ

DQ9

DQ10

DQ23

VDD

VSS

RFU2

VDD

RFU1

VSS

VDD

DQ8

VREF

A10

RAS

RESET

CKE

RFU5

VREF

A11

BA0

CAS

BA1

A8/AP

8M x 32

Configuration

Refresh Count

Bank Address

Row Address

Column Address

AP Flag

2M x 32 x 4 banks

BA0, BA1

A0~A11

A0~A7, A9

Package Top View

(see the balls through the package)

Rev. 1.1 / Sep. 2005

1HY5RS573225F(P)

FUNCTIONAL BLOCK DIAGRAM

4Banks x 2Mbit x 32 I/O Double Data Rate Synchronous DRAM

Rev. 1.1 / Sep. 2005

参数对比

与HY5RS573225FP-18相近的元器件有：HY5RS573225FP-22、HY5RS573225FP-14、HY5RS573225FP-2、HY5RS573225FP-13、HY5RS573225FP-12、HY5RS573225FP-15、HY5RS573225FP-16。描述及对比如下：

型号	HY5RS573225FP-18	HY5RS573225FP-22	HY5RS573225FP-14	HY5RS573225FP-2	HY5RS573225FP-13	HY5RS573225FP-12	HY5RS573225FP-15	HY5RS573225FP-16
描述	DDR DRAM, 8MX32, 0.28ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.3ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.26ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.3ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.25ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.25ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.26ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144	DDR DRAM, 8MX32, 0.28ns, CMOS, PBGA144, 12 X 12 MM, LEAD FREE, FBGA-144
是否Rohs认证	符合	符合	符合	符合	符合	符合	符合	符合
零件包装代码	BGA	BGA	BGA	BGA	BGA	BGA	BGA	BGA
包装说明	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32	LFBGA, BGA144,12X12,32
针数	144	144	144	144	144	144	144	144
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown
ECCN代码	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99	EAR99
访问模式	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
最长访问时间	0.28 ns	0.3 ns	0.26 ns	0.3 ns	0.25 ns	0.25 ns	0.26 ns	0.28 ns
其他特性	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	550 MHz	450 MHz	700 MHz	500 MHz	750 MHz	800 MHz	650 MHz	600 MHz
I/O 类型	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON	COMMON
JESD-30 代码	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144	S-PBGA-B144
长度	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm
内存密度	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit	268435456 bit
内存集成电路类型	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
内存宽度	32	32	32	32	32	32	32	32
功能数量	1	1	1	1	1	1	1	1
端口数量	1	1	1	1	1	1	1	1
端子数量	144	144	144	144	144	144	144	144
字数	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words	8388608 words
字数代码	8000000	8000000	8000000	8000000	8000000	8000000	8000000	8000000
工作模式	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
最高工作温度	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C	85 °C
组织	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32	8MX32
输出特性	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE	3-STATE
封装主体材料	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
封装代码	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA	LFBGA
封装等效代码	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32	BGA144,12X12,32
封装形状	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
封装形式	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）	260	260	260	260	260	260	260	260
电源	2 V	2 V	2 V	2 V	2 V	2 V	2 V	2 V
认证状态	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
刷新周期	4096	4096	4096	4096	4096	4096	4096	4096
座面最大高度	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm	1.3 mm
自我刷新	YES	YES	YES	YES	YES	YES	YES	YES
连续突发长度	4	4	4	4	4	4	4	4
最大待机电流	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A	0.03 A
最大压摆率	1.05 mA	0.95 mA	1.2 mA	1 mA	1.25 mA	1.3 mA	1.15 mA	1.1 mA
最大供电电压 (Vsup)	2.1 V	2.1 V	2.1 V	2.1 V	2.1 V	2.1 V	2.1 V	2.1 V
最小供电电压 (Vsup)	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V	1.9 V
标称供电电压 (Vsup)	2 V	2 V	2 V	2 V	2 V	2 V	2 V	2 V
表面贴装	YES	YES	YES	YES	YES	YES	YES	YES
技术	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
温度等级	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER	OTHER
端子形式	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
端子节距	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm	0.8 mm
端子位置	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
处于峰值回流温度下的最长时间	20	20	20	20	20	20	20	20
宽度	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm	12 mm
厂商名称	SK Hynix(海力士)	SK Hynix(海力士)	-	-	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)	SK Hynix(海力士)