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K4S161622D-TL80

Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50

器件类别：存储    存储   

厂商名称：SAMSUNG(三星)

厂商官网：http://www.samsung.com/Products/Semiconductor/

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参数 预览 参数对比
器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
SAMSUNG(三星)
Objectid
1507078623
零件包装代码
TSOP2
包装说明
TSOP2, TSOP50,.46,32
针数
50
Reach Compliance Code
compliant
ECCN代码
EAR99
compound_id
9846624
访问模式
DUAL BANK PAGE BURST
最长访问时间
6 ns
其他特性
AUTO/SELF REFRESH
最大时钟频率 (fCLK)
125 MHz
I/O 类型
COMMON
交错的突发长度
1,2,4,8
JESD-30 代码
R-PDSO-G50
JESD-609代码
e0
长度
20.95 mm
内存密度
16777216 bit
内存集成电路类型
SYNCHRONOUS DRAM
内存宽度
16
功能数量
1
端口数量
1
端子数量
50
字数
1048576 words
字数代码
1000000
工作模式
SYNCHRONOUS
最高工作温度
70 °C
最低工作温度
组织
1MX16
输出特性
3-STATE
封装主体材料
PLASTIC/EPOXY
封装代码
TSOP2
封装等效代码
TSOP50,.46,32
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, THIN PROFILE
电源
3.3 V
认证状态
Not Qualified
刷新周期
2048
座面最大高度
1.2 mm
自我刷新
YES
连续突发长度
1,2,4,8,FP
最大待机电流
0.002 A
最大压摆率
0.13 mA
最大供电电压 (Vsup)
3.6 V
最小供电电压 (Vsup)
3 V
标称供电电压 (Vsup)
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.8 mm
端子位置
DUAL
宽度
10.16 mm
文档预览
K4S161622D
CMOS SDRAM
1M x 16 SDRAM
512K x 16bit x 2 Banks
Synchronous DRAM
LVTTL
Revision 1.5
September 2000
Samsung Electronics reserves the right to change products or specification without notice.
Rev 1.5 Sep. '00
K4S161622D
Revision History
Revision 1.5 (September 22, 2000)
• Removed -8.7ns@CL2 in K4S161622D-70.
CMOS SDRAM
Rev 1.5 Sep. '00
K4S161622D
512K x 16Bit x 2 Banks Synchronous DRAM
FEATURES
•
•
•
•
3.3V power supply
LVTTL compatible with multiplexed address
Dual banks operation
MRS cycle with address key programs
-. CAS Latency ( 2 & 3)
-. Burst Length (1, 2, 4, 8 & full page)
-. Burst Type (Sequential & Interleave)
All inputs are sampled at the positive going edge of the system
clock
Burst Read Single-bit Write operation
DQM for masking
Auto & self refresh
15.6us refresh duty cycle (2K/32ms)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
•
•
•
•
•
ORDERING INFORMATION
Part NO.
K4S161622D-TC/L55
K4S161622D-TC/L60
K4S161622D-TC/L70
K4S161622D-TC/L80
K4S161622D-TC/L10
MAX Freq.
183MHz
166MHz
143MHz
125MHz
100MHz
LVTTL
50
TSOP(II)
Interface Package
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
Refresh Counter
Output Buffer
Row Decoder
Sense AMP
512K x 16
Row Buffer
DQi
Address Register
CLK
ADD
512K x 16
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to
change products or specification without
notice.
Rev 1.5 Sep. '00
K4S161622D
PIN CONFIGURATION
(TOP VIEW)
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
50PIN TSOP (II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System Clock
Chip Select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row / column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
10
, column address : CA
0
~ CA
7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock Enable
A
0
~ A
10
/AP
BA
RAS
CAS
WE
L(U)DQM
DQ
0
~
15
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank Select Address
Row Address Strobe
Column Address Strobe
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection/
Reserved for Future Use
Rev 1.5 Sep. '00
K4S161622D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high votlage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
Note
4
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note :
1. V
IH
(max) = 5.6V AC. The overshoot voltage duration is
≤
3ns.
:
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. The VDD condition of K4S161622D-55/60 is 3.135V~3.6V.
CAPACITANCE
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2
2
2
3
Max
4
4
4
5
Unit
pF
pF
pF
pF
Clock
RAS, CAS, WE, CS, CKE, L(U)DQM
Address
DQ
0
~ DQ
15
DECOUPLING CAPACITANCE GUIDE LINE
Recommended decoupling capacitance added to power line at board.
Parameter
Decoupling Capacitance between V
DD
and V
SS
Decoupling Capacitance between V
DDQ
and V
SSQ
Symbol
C
DC1
C
DC2
Value
0.1 + 0.01
0.1 + 0.01
Unit
uF
uF
Note :
1. V
DD
and V
DDQ
pins are separated each other.
All V
DD
pins are connected in chip. All V
DDQ
pins are connected in chip.
2. V
SS
and V
SSQ
pins are separated each other
All V
SS
pins are connected in chip. All V
SSQ
pins are connected in chip.
Rev 1.5 Sep. '00
查看更多>
参数对比
与K4S161622D-TL80相近的元器件有：K4S161622D-TL55、K4S161622D-TC10、K4S161622D-TC70、K4S161622D-TL10、K4S161622D-TL60、K4S161622D-TC80、K4S161622D-TC60、K4S161622D-TC55、K4S161622D-TL70。描述及对比如下：
型号 K4S161622D-TL80 K4S161622D-TL55 K4S161622D-TC10 K4S161622D-TC70 K4S161622D-TL10 K4S161622D-TL60 K4S161622D-TC80 K4S161622D-TC60 K4S161622D-TC55 K4S161622D-TL70
描述 Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 6ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50 Synchronous DRAM, 1MX16, 5.5ns, CMOS, PDSO50, 0.400 X 0.825 INCH, 0.80 MM PITCH, TSOP2-50
是否Rohs认证 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合 不符合
厂商名称 SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星) SAMSUNG(三星)
零件包装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
包装说明 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32 TSOP2, TSOP50,.46,32
针数 50 50 50 50 50 50 50 50 50 50
Reach Compliance Code compliant compliant compliant compliant compliant compliant compliant compliant compliant compli
ECCN代码 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
访问模式 DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST DUAL BANK PAGE BURST
最长访问时间 6 ns 5 ns 6 ns 5.5 ns 6 ns 5.5 ns 6 ns 5.5 ns 5 ns 5.5 ns
其他特性 AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
最大时钟频率 (fCLK) 125 MHz 183 MHz 100 MHz 143 MHz 100 MHz 166 MHz 125 MHz 166 MHz 183 MHz 143 MHz
I/O 类型 COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON COMMON
交错的突发长度 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8 1,2,4,8
JESD-30 代码 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50 R-PDSO-G50
JESD-609代码 e0 e0 e0 e0 e0 e0 e0 e0 e0 e0
长度 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm 20.95 mm
内存密度 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bit 16777216 bi
内存集成电路类型 SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
内存宽度 16 16 16 16 16 16 16 16 16 16
功能数量 1 1 1 1 1 1 1 1 1 1
端口数量 1 1 1 1 1 1 1 1 1 1
端子数量 50 50 50 50 50 50 50 50 50 50
字数 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words 1048576 words
字数代码 1000000 1000000 1000000 1000000 1000000 1000000 1000000 1000000 1000000 1000000
工作模式 SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
最高工作温度 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
组织 1MX16 1MX16 1MX16 1MX16 1MX16 1MX16 1MX16 1MX16 1MX16 1MX16
输出特性 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2 TSOP2
封装等效代码 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32 TSOP50,.46,32
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE SMALL OUTLINE, THIN PROFILE
电源 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
认证状态 Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
刷新周期 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048
座面最大高度 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm 1.2 mm
自我刷新 YES YES YES YES YES YES YES YES YES YES
连续突发长度 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP 1,2,4,8,FP
最大待机电流 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A 0.002 A
最大压摆率 0.13 mA 0.155 mA 0.115 mA 0.14 mA 0.115 mA 0.15 mA 0.13 mA 0.15 mA 0.155 mA 0.14 mA
最大供电电压 (Vsup) 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
最小供电电压 (Vsup) 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V 3 V
标称供电电压 (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES YES YES YES YES YES YES YES
技术 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
端子节距 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
端子位置 DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL DUAL
宽度 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm 10.16 mm
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器件捷径:
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF AG AH AI AJ AK AL AM AN AO AP AQ AR AS AT AU AV AW AX AY AZ B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF BG BH BI BJ BK BL BM BN BO BP BQ BR BS BT BU BV BW BX BY BZ C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF CG CH CI CJ CK CL CM CN CO CP CQ CR CS CT CU CV CW CX CY CZ D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF DG DH DI DJ DK DL DM DN DO DP DQ DR DS DT DU DV DW DX DZ
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