ferrite beads, shielding and other passive components that
are traditionally required to pass EMI regulations.
The P1819 modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more
importantly,
decreases
the
peak
amplitudes
of
its
harmonics. This results in significantly lower system EMI
compared to the typical narrow band signal produced by
oscillators and most frequency generators. Lowering EMI
by increasing a signal’s bandwidth is called ‘Spread
Spectrum Clock Generation’.
The P1819 is available in different spread deviation, refer
to “Spread Deviation Selection” Table.
The P1819 uses the most efficient and optimized
modulation
profile
approved
by
the
FCC
and
is
implemented in a proprietary all digital method.
Applications
The P1819 is targeted towards EMI management for
memory and LVDS interfaces in mobile graphic chipsets
and high-speed digital applications such as PC peripheral
devices, consumer electronics, and embedded controller
systems.
Product Description
The P1819 is a Versatile Spread Spectrum Frequency
Modulator designed specifically for input clock frequencies
from 20 to 40MHz. (Refer
Input Frequency and Modulation
Rate
Table).
The
P1819
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of
down stream clock and data
dependent signals. The P1819 allows significant system
cost savings by reducing the number of circuit board layers
Block Diagram
D_C/NC PD# SRS
VDD
Modulation
XIN/CLKIN
Crystal
Oscillator
XOUT
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
REF
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
March 2007
rev 1.9
Pin Configuration
XIN/ CLKIN
VSS
SRS
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
XIN / CLKIN
VSS
D_C / NC
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
P1819
P1819 A/B/C/D
P1819 E/F/G/H/Q
Pin Description
Pin#
1819A/B/C/D
1
2
3
1819E/F/G/H/Q
1
2
Pin Name
Type
Description
Crystal Connection or external frequency input.This pin
has dual functions. It can be connected to either an
external crystal or an external reference clock
Ground Connection. Connect to system ground.
Spread range select. Digital logic input used to select
frequency deviation
(Refer Spread Deviation Selection
Table).
This pin has an internal pull-up resistor.
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options (Refer
Spread Deviation
Selection Table).
This pin has an internal pull-up
resistor.
Spread spectrum clock output.
(Refer Input Frequency
and Modulation Rate Table and Spread Deviation
Selection Table)
Non-modulated Reference clock output of the input
frequency.
Power down control pin. Pull XIN/CLKIN and PD# LOW
to enable Power-Down mode. This pin has an internal
pull-up resistor.
Power Supply for the entire chip.
Crystal Connection. Input connection for an external
crystal. If using an external reference, this pin must be
left unconnected.
XIN / CLKIN
VSS
SRS
I
P
I
3
3
D_C / NC
I
4
5
6
7
8
Note: Pin 3 is NC in P1819Q
4
5
6
7
8
ModOUT
REF
PD#
VDD
XOUT
O
O
I
P
O
Input Frequency and Modulation Rate
Part Number
P1819
Input Frequency Range
20MHz to 40MHz
Output Frequency range
20MHz to 40MHz
Modulation rate
Input Frequency / 896
Note Book LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
2 of 8
March 2007
rev 1.9
Spread Deviation Selection
Part Number
P1819A
P1819
SRS
0
1
0
1
0
1
0
1
NA
D_C
NA
Spread Deviation
-2.50% (DOWN)
-3.50% (DOWN)
-1.25% (DOWN)
-1.75% (DOWN)
±1.25% (CENTER)
±1.75% (CENTER)
±0.625% (CENTER)
±0.875% (CENTER)
-1.25% (DOWN)
±0.625% (CENTER)
-2.5% (DOWN)
±1.25% (CENTER)
-1.75% (DOWN)
±0.875% (CENTER)
-3.5% (DOWN)
±1.75% (CENTER)
-2.5% (DOWN)
P1819B
NA
P1819C
NA
P1819D
NA
0
1
0
1
0
1
0
1
NA
P1819E
P1819F
NA
P1819G
NA
P1819H
P1819Q
NA
NA
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +7.0
-65 to +125
0 to 70
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Note Book LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
3 of 8
March 2007
rev 1.9
DC Electrical Characteristics
(Test condition: All parameters are measured at room temperature (+25°C) unless otherwise stated)
P1819
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
CC
I
DD
V
DD
t
ON
Z
OUT
Input Low voltage
Input High voltage
Parameter
Min
VSS – 0.3
2.0
-60.0
Typ
Max
0.8
V
DD
+ 0.3
-20.0
1.0
Unit
V
V
µA
µA
mA
mA
V
V
mA
mA
Input Low current (inputs D_C, PD#, SRS)
Input High current
X
OUT
Output low current @ 0.4V, V
DD
= 3.3V
X
OUT
Output high current @ 2.5V, V
DD
= 3.3V
Output Low voltage V
DD
= 3.3V, I
OL
= 20mA
Output High voltage V
DD
= 3.3V, I
OH
= 20mA
Dynamic supply current normal mode
3.3V and 25pF probe loading
Static supply current standby mode
Operating Voltage
Power up time (first locked clock cycle after power up)
Clock Output impedance
2.0
12.0
12.0
0.4
2.5
7.1
f
IN - min
4.5
3.0
3.3
0.18
50
-
26.9
f
IN - max
3.6
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
*
t
HL
*
t
JC
t
LTJ
t
D
Parameter
Input Frequency
Output Frequency
Output Rise time
Measured from 0.8V to 2.0V
Output Fall time
Measured from 2.0V to 0.8V
Jitter (cycle to cycle)
Long Term Jitter,(1000 cycle) on
Refout @ 27MHz
Output Duty cycle
Min
20
20
Typ
Max
40
40
Unit
MHz
MHz
nS
nS
0.66
0.65
-200
475
45
50
55
200
pS
pS
%
*t
LH
and t
HL
are measured into a capacitive load of 15pF
Note Book LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
4 of 8
March 2007
rev 1.9
P1819
Package Information
8-Pin SOIC Package
E
H
D
A2
A
θ
e
B
A
1
C
L
D
Dimensions
Symbol
Min
A1
A
A2
B
C
D
E
e
H
L
θ
Inches
Max
0.010
0.069
0.059
0.020
0.010
0.004
0.053
0.049
0.012
0.007
Millimeters
Min
Max
0.10
1.35
1.25
0.31
0.18
4.90 BSC
3.91 BSC
1.27 BSC
6.00 BSC
0.41
0°
1.27
8°
0.25
1.75
1.50
0.51
0.25
0.193 BSC
0.154 BSC
0.050 BSC
0.236 BSC
0.016
0°
0.050
8°
Note: Controlling dimensions are millimeters
SOIC – 0.074 grams unit weight
Note Book LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
