MAN-000643-000
Rev. 1.3
October 11, 1999
PCI0643
Bus Master DMA
PCI-IDE Chip Specification
CMD Technology, Inc.
19 Morgan
Irvine, California 92618
(949) 454-0800
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Table of Contents
1
Chip Structure
1.1 Pin Descriptions
1.2 Register Definition
1.2.1 Standard Configuration Header
1.2.2 Base Address Registers
1.2.3 Status/Command Register (04h)
1.2.4 Configuration Registers
1.2.5 IDE Timing Control Registers
1.3 PCI Master Control Registers
1.4 Active Count Function
1.5 Recovery Count Function
1.6 Task File Registers
1.7 Configuration Setup
1.7.1 Notes
1.7.2 Configuration Mechanism #2
1.8 PIO Mode Interrupt Processing
1.9 DMA Programming
1.10
Read Ahead Operation
1.11
PCI0643 IDE Controller Pinout
1.11.1 Host Interface Pinout
1.11.2 Drive Interface Pinout
1.11.3 VDD/VSS Pins
1.12
Pinout Diagram
1.13
100-Pin TQFP Dimensions
1.14
Jumper Settings
Power Specifications
2.1 DC Specifications
2.1.1 Maximum Ratings
2.1.2 Recommended Operating Conditions (Vss = 0V)
2.2 DC Characteristics
2.3 AC Specifications
2.3.1 Timing Waveform
2.3.2 Clock Timing
2.3.3 Host Interface Timing (loading = 50 pf)
2.3.4 IDE Drive Timing (loading = 75 pf)
2.3.5 IDE Drive Timing (loading = 120 pf)
2.4 Output Test Load
1
1
7
7
7
8
9
9
12
15
15
16
16
16
16
16
17
17
18
18
19
20
21
22
23
23
23
23
23
23
24
24
24
24
24
25
25
2
iii
Table of Contents
PCI0643
2.5 IDE Write Timing
2.6 Host Read/Write Timing
2.7 PCI Read/Write Timing in Target Mode
2.8 IDE Timing
2.9 PCI DMA Master Read Timing (33MHz PCICLK)
2.10
PCI DMA Master Write Timing (33MHz PCICLK)
25
26
26
27
28
29
iv
PCI0643
1
Chip Structure
1.1
Pin Descriptions
The following is an alphabetical listing of PCI mode signals and their pin assignments. A
numerically sorted pinout may be found on page 18. Please refer to the PCI mode pinout
diagram for the locations of the pins.
Signal
2NDIDEEN#/DMACK0#
Function
This signal normally is used in response to DMARQ0 to either acknowledge that data has
been accepted, or that data is available. At power-up reset, the state of this signal is used
to enable or disable the secondary channel.
Pin
87
Type
B/T
Signal
2NDIOR#
Function
Pin
77
Type
T/O
Secondary Channel Disk IO Read is an active low output which enables data to be read
from the drive. The duration and repetition rate of DIOR# cycles is determined by PCI0643
programming. DIOR# is driven high when inactive.
Signal
2NDIOW#
Function
Pin
78
Type
T/O
Secondary Channel Disk I/O Write is an active low output that enables data to be written to
the drive. The duration and repetition rate of DIOW# cycles is determined by PCI0643
programming. DIOW# is driven high when inactive.
Signal
AD[31..0]
Function
Pins
7-14, 17-20, 23-26, 28-35, 42-49
Type
B/T
Address and Data are multiplexed on the same PCI pins. A bus transaction consists of an
address phase followed by one or more data phases. PCI supports both read and write
bursts. The address phase is the clock cycle in which FRAME # is asserted. During the
address phase AD[31..0] contain a physical address (32 bits). For I/O, this is a byte
address; for configuration and memory it is a DWORD address. During data phases
AD[7..0] contain the least significant byte (lsb) and AD[31..24] contain the most significant
byte (msb). Write data are stable and valid when IRDY# is asserted and read data are
stable and valid when TRDY# is asserted. Data are transferred during those clocks where
both IRDY# and TRDY# are asserted.
Signal
C/BE[3..0]#
Function
Pins
3-6
Type
B/T
Byte Enable bits 0 through 3 form the host CPU address bus. These inputs are active low
and specify which bytes will be valid for master read/write data transfers.
Chip Structure
1
