PHT6N06T
TrenchMOS™ standard level FET
M3D087
Rev. 02 — 03 February 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect transistor in a plastic package using
TrenchMOS™ technology.
Product availability:
PHT6N06T in SOT223.
1.2 Features
s
Low on-state resistance
s
Fast switching
s
Low Q
GD
s
Surface mounting package.
1.3 Applications
s
DC to DC converters
s
General purpose switching.
1.4 Quick reference data
s
V
DS
≤
55 V
s
P
tot
≤
8.3 W
s
I
D
≤
5.5 A
s
R
DSon
≤
150 mΩ
2. Pinning information
Table 1:
Pin
1
2
3
4
Pinning - SOT223, simplified outline and symbol
Description
gate (g)
drain (d)
source (s)
drain (d)
g
s
Simplified outline
4
Symbol
d
MBB076
1
Top view
2
3
MSB002 - 1
SOT223
Philips Semiconductors
PHT6N06T
TrenchMOS™ standard level FET
3. Limiting values
Table 2:
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
V
DS
V
DGR
V
GS
I
D
I
DM
P
tot
T
stg
T
j
I
S
I
SM
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
peak drain current
total power dissipation
storage temperature
junction temperature
source (diode forward) current (DC) T
sp
= 25
°C
peak source (diode forward) current T
sp
= 25
°C;
pulsed; t
p
≤
10
µs
T
sp
= 25
°C;
V
GS
= 10 V;
Figure 2
and
3
T
sp
= 100
°C;
V
GS
= 10 V;
Figure 2
T
sp
= 25
°C;
pulsed; t
p
≤
10
µs;
Figure 3
T
sp
= 25
°C;
Figure 1
Conditions
25
°C ≤
T
j
≤
150
°C
25
°C ≤
T
j
≤
150
°C;
R
GS
= 20 kΩ
Min
-
-
-
-
-
-
-
−55
−55
-
-
Max
55
55
±20
5.5
3.8
22
8.3
+150
+150
5.5
22
Unit
V
V
V
A
A
A
W
°C
°C
A
A
Source-drain diode
9397 750 10633
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 03 February 2003
2 of 12
Philips Semiconductors
PHT6N06T
TrenchMOS™ standard level FET
120
Pder
(%)
80
03aa17
120
Ider
(%)
80
03aa25
40
40
0
0
50
100
150
Tsp (°C)
200
0
0
50
100
150
200
Tsp (
°
C)
P
tot
P
der
=
----------------------
×
100%
-
P
°
tot
(
25 C
)
V
GS
≥
10 V
I
D
I
der
=
-------------------
×
100%
I
°
D
(
25 C
)
Fig 1. Normalized total power dissipation as a
function of solder point temperature.
Fig 2. Normalized continuous drain current as a
function of solder point temperature.
102
ID
(A)
10
Limit RDSon = VDS/ID
003aaa313
tp = 10
µs
100
µs
1 ms
DC
10 ms
100 ms
1
10-1
10-2
1
10
VDS (V)
102
T
sp
= 25
°C;
I
DM
is single pulse; V
GS
= 10 V.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 10633
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 03 February 2003
3 of 12
Philips Semiconductors
PHT6N06T
TrenchMOS™ standard level FET
4. Thermal characteristics
Table 3:
R
th(j-sp)
R
th(j-a)
Thermal characteristics
Conditions
Figure 4
Min
-
Typ
-
70
Max
15
-
Unit
K/W
K/W
thermal resistance from junction to solder point
thermal resistance from junction to ambient
Symbol Parameter
minimum footprint; mounted on a -
printed-circuit board
4.1 Transient thermal impedance
102
003aaa314
Zth(j-sp)
(K/W)
10
δ
= 0.5
0.2
0.1
1
0.05
0.02
single pulse
10-1
P
δ
=
tp
T
tp
t
T
10-2
10-6
10-5
10-4
10-3
10-2
10-1
1
tp (s)
10
Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration.
9397 750 10633
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 03 February 2003
4 of 12
Philips Semiconductors
PHT6N06T
TrenchMOS™ standard level FET
5. Characteristics
Table 4:
Characteristics
T
j
= 25
°
C unless otherwise specified.
Symbol Parameter
Static characteristics
V
(BR)DSS
drain-source breakdown voltage
I
D
= 250
µA;
V
GS
= 0 V
T
j
= 25
°C
T
j
=
−55 °C
V
GS(th)
gate-source threshold voltage
I
D
= 1 mA; V
DS
= V
GS
;
Figure 9
T
j
= 25
°C
T
j
= 150
°C
T
j
=
−55 °C
I
DSS
drain-source leakage current
V
DS
= 55 V; V
GS
= 0 V
T
j
= 25
°C
T
j
= 150
°C
I
GSS
R
DSon
gate-source leakage current
drain-source on-state resistance
V
GS
=
±20
V; V
DS
= 0 V
V
GS
= 10 V; I
D
= 5 A;
Figure 7
and
8
T
j
= 25
°C
T
j
= 150
°C
Dynamic characteristics
Q
g(tot)
Q
gs
Q
gd
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain (Miller) charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain (diode forward) voltage I
S
= 5 A; V
GS
= 0 V;
Figure 12
reverse recovery time
recovered charge
I
S
= 5 A; dI
S
/dt =
−100
A/µs; V
GS
= 0 V;
V
R
= 30 V
V
DD
= 30 V; I
D
= 5 A; V
GS
= 10 V; R
G
= 6
Ω
V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz;
Figure 11
I
D
= 5 A; V
DD
= 44 V; V
GS
= 10 V;
Figure 13
-
-
-
-
-
-
-
-
-
-
-
-
-
5.6
1.2
2.6
175
58
40
4.9
14.5
7.8
4.5
0.85
32
50
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
-
-
128
-
150
278
mΩ
mΩ
-
-
-
0.05
-
2
10
500
100
µA
µA
nA
2
1.2
−
3
−
−
4
−
4.4
55
50
-
-
-
-
V
V
V
V
V
V
Conditions
Min
Typ
Max
Unit
Source-drain diode
9397 750 10633
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 03 February 2003
5 of 12
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