b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation
process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder intercon-
nection.
c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71657
S-21251—Rev. B, 05-Aug-02
www.vishay.com
2-1
Si5406DC
Vishay Siliconix
SPECIFICATIONS (T
J
= 25_C UNLESS OTHERWISE NOTED)
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
Zero Gate Voltage Drain Current
On-State Drain Current
a
Drain-Source On-State Resistance
a
Forward Transconductance
a
Diode Forward Voltage
a
V
GS(th)
I
GSS
I
DSS
I
D(on)
r
DS(on)
g
fs
V
SD
V
DS
= V
GS
, I
D
= 1.2 mA
V
DS
= 0 V, V
GS
=
8
V
V
DS
= 9.6 V, V
GS
= 0 V
V
DS
= 9.6 V, V
GS
= 0 V, T
J
= 85_C
V
DS
≥
5 V, V
GS
= 4.5 V
V
GS
= 4.5 V, I
D
= 6.9 A
V
GS
= 2.5 V, I
D
= 2 A
V
DS
= 10 V, I
D
= 6.9 A
I
S
= 1.1 A, V
GS
= 0 V
20
0.017
0.021
30
0.7
1.2
0.020
0.025
0.6
100
1
5
V
nA
mA
A
Ω
S
V
Symbol
Test Condition
Min
Typ
Max
Unit
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
I
F
= 1.1 A, di/dt = 100 A/ms
V
DD
= 6 V, R
L
= 6
Ω
I
D
≅
1 A, V
GEN
= 4.5 V, R
G
= 6
Ω
V
DS
= 6 V, V
GS
= 4.5 V, I
D
= 6.9 A
13.7
2.3
4.1
17
46
54
29
35
25
70
80
45
70
ns
20
nC
Notes
a. Pulse test; pulse width
≤
300
ms,
duty cycle
≤
2%.
b. Guaranteed by design, not subject to production testing.
