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SSM6J412TU

Power Management Switch Applications

器件类别:分立半导体    晶体管   

厂商名称:Toshiba(东芝)

厂商官网:http://toshiba-semicon-storage.com/

器件标准:

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器件参数
参数名称
属性值
是否Rohs认证
符合
厂商名称
Toshiba(东芝)
包装说明
SMALL OUTLINE, R-PDSO-F6
针数
6
Reach Compliance Code
unknow
ECCN代码
EAR99
配置
SINGLE WITH BUILT-IN DIODE
最小漏源击穿电压
20 V
最大漏极电流 (ID)
4 A
最大漏源导通电阻
0.0427 Ω
FET 技术
METAL-OXIDE SEMICONDUCTOR
JESD-30 代码
R-PDSO-F6
元件数量
1
端子数量
6
工作模式
ENHANCEMENT MODE
封装主体材料
PLASTIC/EPOXY
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE
峰值回流温度(摄氏度)
NOT SPECIFIED
极性/信道类型
P-CHANNEL
认证状态
Not Qualified
表面贴装
YES
端子形式
FLAT
端子位置
DUAL
处于峰值回流温度下的最长时间
NOT SPECIFIED
晶体管应用
SWITCHING
晶体管元件材料
SILICON
文档预览
SSM6J412TU
TOSHIBA Field-Effect Transistor Silicon P-Channel MOS Type (U-MOSⅥ)
SSM6J412TU
Power Management Switch Applications
1.5-V drive
Low ON-resistance: R
DS(ON)
= 99.6 mΩ (max) (@V
GS
= -1.5 V)
R
DS(ON)
= 67.8 mΩ (max) (@V
GS
= -1.8 V)
R
DS(ON)
= 51.4 mΩ (max) (@V
GS
= -2.5 V)
R
DS(ON)
= 42.7 mΩ (max) (@V
GS
= -4.5 V)
2.1±0.1
1.7±0.1
0.65 0.65
+0.1
0.3-0.05
Unit: mm
2.0±0.1
1.3±0.1
1
2
3
6
5
4
Absolute Maximum Ratings
(Ta = 25°C)
Drain-source voltage
Gate-source voltage
Drain current
Power dissipation
Channel temperature
Storage temperature range
DC
Pulse
V
DSS
V
GSS
I
D
I
DP
(Note 1)
P
D
(Note 2)
T
ch
T
stg
-20
±
8
-4.0
-16.0
1
150
−55
to 150
V
V
A
W
°C
°C
0.7±0.05
UF6
1,2,5,6: Drain
3:
Gate
4:
Source
JEDEC
Note: Using continuously under heavy loads (e.g. the application of high
temperature/current/voltage and the significant change in
JEITA
temperature, etc.) may cause this product to decrease in the
TOSHIBA
2-2T1D
reliability significantly even if the operating conditions (i.e.
operating temperature/current/voltage, etc.) are within the
Weight : 7.0mg ( typ. )
absolute maximum ratings.
Please design the appropriate reliability upon reviewing the
Toshiba Semiconductor Reliability Handbook (“Handling Precautions”/“Derating Concept and Methods”) and
individual reliability data (i.e. reliability test report and estimated failure rate, etc).
Note 1: Pw
10μs, Duty.
1%
Note 2: Mounted on a FR4 board.
(25.4 mm
×
25.4 mm
×
1.6 mm , Cu Pad: 645 mm
2
)
Marking (Top View)
6
5
4
Equivalent Circuit
6
5
4
KPH
1
2
3
1
2
3
1
2010-12-08
+0.06
0.16-0.05
Characteristic
Symbol
Rating
Unit
SSM6J412TU
Electrical Characteristics
(Ta = 25°C)
Characteristic
Drain-source breakdown voltage
Drain cut-off current
Gate leakage current
Gate threshold voltage
Forward transfer admittance
Symbol
Test Conditions
Min
-20
(Note 4)
-15
-0.3
(Note 3)
(Note 3)
(Note 3)
(Note 3)
(Note 3)
4.5
(Note 3)
Typ.
9.1
36.9
42.8
50.6
58.6
840
118
99
32
107
12.8
1.4
3.0
0.88
Max
-1
±1
-1.0
42.7
51.4
67.8
99.6
1.2
V
nC
ns
pF
Unit
V
V
μA
μA
V
S
V
(BR) DSS
I
D
= -1 mA, V
GS
= 0 V
V
(BR) DSX
I
D
= -1 mA, V
GS
= 5 V
I
DSS
I
GSS
V
th
⏐Y
fs
V
DS
= -20 V, V
GS
= 0 V
V
GS
=
±8
V, V
DS
= 0 V
V
DS
= -3 V, I
D
= -1 mA
V
DS
= -3 V, I
D
= -1.0 A
I
D
= -3.0 A, V
GS
= -4.5 V
Drain–source ON-resistance
R
DS (ON)
I
D
= -2.5 A, V
GS
= -2.5 V
I
D
= -1.5 A, V
GS
= -1.8 V
I
D
= -0.5 A, V
GS
= -1.5 V
Input capacitance
Output capacitance
Reverse transfer capacitance
Switching time
Total gate charge
Gate-source charge
Gate-drain charge
Drain-source forward voltage
Turn-on time
Turn-off time
C
iss
C
oss
C
rss
t
on
t
off
Q
g
Q
gs1
Q
gd
V
DSF
V
DS
= -10 V, V
GS
= 0 V
f = 1 MHz
V
DD
= -10 V, I
D
= -2.0 A
V
GS
= 0 to -2.5 V, R
G
= 4.7
Ω
V
DD
= -10 V, I
D
= -4.0 A,
V
GS
= -4.5 V
I
D
= 4.0 A, V
GS
= 0 V
Note 3: Pulse test
Note 4: If a forward bias is applied between gate and source, this device enters V(BR)DSX mode. Note that the
drain-source breakdown voltage is lowered in this mode.
Switching Time Test Circuit
(a) Test Circuit
(b) V
IN
0
OUT
IN
−2.5
V
R
G
R
L
V
DD
V
DD
t
on
10%
0V
90%
2.5V
10
μs
(c) V
OUT
V
DS (ON)
90%
10%
t
r
t
off
t
f
V
DD
= -10 V
R
G
= 4.7
Ω
Duty
1%
V
IN
: t
r
, t
f
< 5 ns
Common Source
Ta = 25°C
Notice on Usage
V
th
can be expressed as the voltage between gate and source when the low operating current value is I
D
= -1 mA for
this product. For normal switching operation, V
GS (on)
requires a higher voltage than V
th
and V
GS (off)
requires a lower
voltage than V
th.
(The relationship can be established as follows: V
GS (off)
< V
th
< V
GS (on).
)
Take this into consideration when using the device.
Handling Precaution
When handling individual devices that are not yet mounted on a circuit board, make sure that the environment is
protected against electrostatic discharge. Operators should wear antistatic clothing, and containers and other objects that
come into direct contact with devices should be made of antistatic materials.
Thermal resistance R
th (ch-a)
and power dissipation P
D
vary depending on board material, board area, board thickness
and pad area. When using this device, please take heat dissipation into consideration
2
2010-12-08
SSM6J412TU
I
D
– V
DS
-10
VGS
=-4.5
V
-2.5 V
-100
-1.8 V
-10
-1.5 V
-6
Common Source
VDS
=
-3 V
Pulse test
I
D
– V
GS
(A)
-8
(A)
Drain current
I
D
-1
-0.1
Ta
=
100 °C
-0.01
−25
°C
Drain current
I
D
-4
-2
0
Common Source
Ta
=
25 °C
Pulse test
0
-0.2
-0.4
-0.6
-0.8
-1
-0.001
25 °C
-0.0001
0
-0.5
-1.0
-1.5
-2.0
Drain–source voltage
V
DS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– V
GS
140
120
ID =-0.5A
Common Source
Pulse test
140
120
R
DS (ON)
– V
GS
ID =-2.5A
Common Source
Pulse test
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
40
Drain–source ON-resistance
R
DS (ON)
(mΩ)
100
80
60
40
Ta
=
100 °C
25 °C
Ta
=
100 °C
25 °C
20
0
25 °C
0
-2
-4
-6
-8
20
0
25 °C
0
-2
-4
-6
-8
Gate–source voltage
V
GS
(V)
Gate–source voltage
V
GS
(V)
R
DS (ON)
– I
D
140
120
140
Common Source
Ta = 25°C
120
Common Source
Pulse test
R
DS (ON)
– Ta
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Drain–source ON-resistance
R
DS (ON)
(mΩ)
Pulse test
VGS
=
-1.5 V
100
80
100
-1.5 A / -1.8 V
-2.5 A / -2.5 V
ID
=
-0.5 A / VGS
=
-1.5 V
80
60
40
-1.8 V
60
-2.5 V
40
20
0
-4.5 V
-3.0 A / -4.5 V
20
0
−50
0
-2.0
-4.0
-6.0
-8.0
-10.0
0
50
100
150
Drain current
I
D
(A)
Ambient temperature
Ta
(°C)
3
2010-12-08
SSM6J412TU
V
th
– Ta
Common Source
VDS = -3 V
ID = -1 mA
(S)
-1.0
|Y
fs
| – I
D
100
Common Source
30
VDS
=
-3 V
Ta
=
25 °C
Pluse test
V
th
(V)
-0.8
Forward transfer admittance
⎪Y
fs
Gate threshold voltage
10
-0.6
3.0
-0.4
1.0
-0.2
0.3
0
−50
0
50
100
150
0.1
-0.01
-0.1
-1
-10
-100
Ambient temperature
Ta
(°C)
Drain current
I
D
(A)
10000
5000
C – V
DS
-8
Dynamic Input Characteristic
(pF)
3000
Ciss
(V)
-6
1000
500
300
V
GS
C
VDD
=
-10 V
VDD
=
-16 V
Capacitance
Gate–source voltage
-4
100
50
30
Common Source
Ta
=
25 °C
f
=
1 MHz
VGS
=
0 V
-1
-10
Coss
Crss
-2
Common Source
ID
=
-4.0 A
Ta
=
25 °C
0
0
10
20
30
10
-0.1
-100
Drain–source voltage
V
DS
(V)
Total Gate Charge
Qg
(nC)
10000
toff
tf
t – I
D
Common Source
VDD = -10 V
VGS = 0 to -2.5 V
Ta = 25 °C
RG = 4.7Ω
I
DR
– V
DS
100
Common Source
VGS
=
0 V
Ta
=
25 °C
D
Pulse test
I
DR
G
1
(A)
I
DR
10
(ns)
1000
100
Drain reverse current
S
Switching time
t
0.1
ton
10
tr
0.01
100 °C
0.001
0
25 °C
−25
°C
0.4
0.6
0.8
1.0
1.2
1
-0.001
-0.01
-0.1
-1
-10
0.2
Drain current
I
D
(A)
Drain–source voltage
V
DS
(V)
4
2010-12-08
SSM6J412TU
Rth – t
w
Transient thermal impedance Rth (°C/W)
600
1.25
P
D
– T
a
Mounted on FR4 board
(25.4mm
×
25.4mm
×
1.6mm ,
Cu Pad : 645 mm
2
)
DC
100
Power dissipation P
D
(W)
Single pulse
Mounted on FR4 board
1.0
0.75
10
0.5
0.25
1
0.001
2
(25.4 mm
×
25.4 mm
×
1.6 mm, Cu Pad: 645 mm )
0.1
1
10
100
1000
0
-40
-20
0
20
40
60
80
100
120 140
160
0.01
Pulse Width
t
w
(s)
Ambient temperature
Ta
(°C)
5
2010-12-08
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